System, PCB, & Package Design

From Silicon to the Physical World: How Cadence Is Redefining the Future

2026-11-11T05:00:00Z

The next great engineering breakthrough won't come from designing better chips alone. It will come from understanding how everything works together.

Over recent months, I've shared several perspectives on the transformation taking place across Electronic Design Automation (EDA), System Design & Analysis (SDA), and the rapidly evolving data centre industry. One thing is becoming increasingly clear: the traditional boundaries between silicon, electronics, mechanical engineering and the physical environment are disappearing. And I believe Cadence Design Systems is uniquely positioned to help lead this transformation.

From the IC to the Entire Environment

Consider the journey of a modern AI processor. It begins with incredibly sophisticated silicon. But performance doesn't stop at the chip. It depends on advanced packaging, PCB design, signal and power integrity, electromagnetic behaviour, thermal management and ultimately the infrastructure supporting it.

An exceptional semiconductor means little if the system cannot reliably power, cool or operate it. This is where Cadence's increasingly comprehensive technology portfolio becomes particularly exciting.

From Virtuoso, Innovus and Integrity 3D-IC at the silicon and advanced packaging levels, through Allegro X, Sigrity X and Clarity for PCB, signal integrity, power integrity and electromagnetic analysis, to Celsius, Fidelity CFD and the Cadence Reality Digital Twin Platform, we can address engineering challenges across an extraordinary range of physical scales.

And now, following our acquisition of Hexagon's Design and Engineering business, including MSC Nastran and Adams, our capabilities extend significantly further into structural mechanics, dynamics and comprehensive Multiphysics simulation. We're moving beyond traditional EDA towards a far more complete engineering ecosystem.

Cadence's "three-layer cake" approach

The Data Center: Where Everything Converges

Nowhere is this transformation more visible than in AI-driven data centres. Increasing compute density brings enormous challenges in power delivery, heat dissipation, cooling efficiency, reliability and sustainability. Cadence Reality's physics-based digital twin technology enables engineers to simulate and optimise data centre environments before making expensive physical changes.

Our collaborations with NVIDIA, NOKIA, HPE and other technology leaders demonstrate how increasingly sophisticated simulation is becoming fundamental to next-generation AI infrastructure. The opportunity is remarkable: connecting engineering decisions made at the silicon and system level with their consequences in the real-world operating environment.

Three Developments I Believe Will Shape Our Industry

1. Shift Left is becoming essential, not optional. Earlier electrical, thermal, electromagnetic and mechanical analysis can reduce costly redesigns, accelerate development and improve reliability. The earlier we understand physical behaviour, the better our engineering decisions become.
2. Multiphysics convergence is transforming system design. The combination of Cadence's established EDA and SDA technologies with Hexagon D&E's world-class mechanical simulation capabilities creates exciting opportunities to eliminate traditional engineering barriers and develop more comprehensive, connected workflows.
3. AI and digital twins are redefining engineering productivity. From AI-assisted design optimisation to large-scale CFD simulation and predictive data centre modelling, engineers can increasingly explore, test and refine complex systems virtually, improving performance while addressing energy consumption and sustainability.

Technology Alone Is Not Enough

Having worked across both Cadence and Hexagon D&E, and now leading our Systems, PCB and Data Centre teams across EMEA, I've witnessed something equally important. The greatest breakthroughs happen when talented people collaborate across disciplines, challenge conventional thinking and focus relentlessly on customer outcomes.

Our opportunity is not simply to offer outstanding individual products. It is to help customers connect their engineering challenges, reduce complexity and innovate with greater confidence. That requires technical excellence, collaboration, trust and a willingness to think beyond traditional boundaries, and that, to me, is what makes this such an exciting time to be part of Cadence.

A Question for the Engineering Community

As silicon, electronics, mechanical systems and physical environments become increasingly interconnected, what do you believe is the biggest barrier to achieving truly integrated engineering — technology, organisational silos or the way we've traditionally approached design?

I'd genuinely welcome your perspectives.

EuMW2026: Cadence Debuts GPU-Accelerated Clarity 3D Solver Solution

2026-11-02T06:58:00Z

AI-enhanced Cadence technologies excited attendees at European Microwave Week 2026 (EuMW 2026) in London, UK, in October. Key highlights and demonstrations across multiple domains were:

AWR Design Environment: RF analysis and agentic AI capabilities
Virtuoso Heterogeneous Integration (VHI) and ViraStack: newest integration of Agentic AI into custom, analog, and mixed-signal integrated circuit (IC) design
System Design and Analysis (SDA): Multiphysics and signal/power integrity (Si/PI) solutions including Clarity 3D Solver, Allegro X, Sigrity X, and Celsius Thermal Solver
Workflow focus: Solutions enabled engineering teams to design, analyze, optimize, and signoff advanced RF-ICs, monolithic microwave integrated circuits (MMICs), modules, packages, and complete systems

Clarity Solver with GPU-Accelerated 3D Electromagnetics

The latest release of Clarity 3D Solver featuring graphical processing unit (GPU) acceleration debuted at EuMW. When used in combination with Cadence’s Millennium supercomputer, Clarity 3D Solver with GPU features the industry’s first FEM GPU solution, which is equivalent to 1000+ CPU cores with Millennium, 100+ CPUs similar performance per GPU, and up to 75% energy efficiency vs. CPU hardware.

Microwave Journal Interview

Gary Lytle, product management director at Cadence, sat down with Tim Rainier of Microwave Journal to discuss the company’s activities at the show. He commented that Cadence products are now being enabled with AI technology to support compressed design cycles that allow customers to make better products faster, reduce their time to market, and uncover unique designs. AI technology is helping designers look at a broader scope by adding its intelligence to make their existing designs better and faster.

Being introduced at the show is Clarity 3D Solver with GPU acceleration, the first-to-market solution with GPU-accelerated FEM technology that is delivering a 10-15X reduction in Cadence’s already fast simulation times. It is putting our customers in the engineering cockpit, making decisions in real time and being able to update their designs as they go through the process. Watch the video interview here.

Cadence OrCAD X and Allegro X 26.1 Is Now Available

2026-10-22T20:47:00Z

The Cadence OrCAD X and Allegro X 26.1 release is now available from Cadence Downloads, delivering significant enhancements across PCB design, package design, system-level design, simulation, and analysis workflows. Here is a summary of the key updates.

Allegro X PCB Editor and Allegro X APD

IPC-compliant footprint generation from an extensive library of standard templates, with support for automatic footprint regeneration.
Dynamic shape editing through the new Dynamic mode, enabling real-time shape updates and visual feedback during editing.
Component-level Design for Assembly (DFA) checks directly within the layout environment.
Enhancements to X AI routing technologies and new X AI Power/Ground Generator, improving routing productivity.
ECAD-MCAD co-design workflow enhancements that streamline collaboration workflows.
System-level design exploration in 3DX Canvas, with support for multiple boards and system connectivity in a unified 3D environment.
Simplified daisy-chain creation and editing for package designs.
SPICE-compatible RLGC models for advanced analysis workflows.
Parameterized structure creation and reuse for evaluating high-speed design alternatives.

Allegro X System Capture

System-level design enhancements, including support for 3D system exports and MCM board integration.
Integrated analysis enhancements in Layout Mode, including RLGC model extraction and LayoutLink-based reflection analysis workflows.
Reusable reliability parameter libraries for consistent application of validated reliability data across projects.
Preservation of Pulse custom variables in project archives to support design handoff and collaboration workflows.
Productivity improvements through schematic Minimap navigation and workspace window stacking.
Enhanced differential pair creation using Constraint Manager capabilities.
Improved pin delay import workflows with automatic data detection, validation, and pre-import review capabilities.

Enhanced module support and streamlined module management workflows for more efficient selection, management, and reuse of module instances.
Enhanced measurement capabilities for more accurate point-to-point and multi-segment distance measurements.
Customizable Heads-Up Display (HUD) and cursor settings that improve visibility, readability, and navigation.
Flexible pin renumbering capabilities that accelerate footprint creation and updates through support for multiple numbering patterns, numbering formats, and direct pin editing.
Net Override and Rule Set views that simplify constraint management by making it easier to identify overrides, enforce constraint inheritance, and manage net-specific design rules.
Improved visibility controls, streamlined layer navigation, and faster access to display views that enhance design productivity.

PSpice and PSpice Advanced Analysis

Persona-based simulation configuration for faster simulation setup and improved consistency across projects.
Additional component libraries from Murata and TAIYO YUDEN, expanding available simulation content.
Intelligent, condition-based model and subcircuit selection for more flexible and adaptable simulation workflows
Ambient temperature-based resistor derating for enhanced stress (smoke) analysis workflows.
Enhanced high-frequency resistor thermal noise modeling with quantum-corrected calculations.
Generic MATLAB and Tcl measurement functions for advanced custom analysis and verification workflows.

Sigrity X Aurora and Topology Workbench

Signal behavior and analysis improved across multiple connected PCB and package designs.
Multi-design reflection analysis enhanced with reusable System Configuration and LayoutLink files.
DDR measurement reporting optimized for next-generation memory technologies through support for LPDDR6 and HBM4.
Serial-link validation accelerated with multi-channel analysis, comprehensive channel characterization, and PCI Express® Gen 7 compliance support.
Waveform review and debug enhanced with advanced measurements, curve filtering, CSV export, enhanced result management, and the new Grid Curve Viewer for side-by-side waveform analysis.
Circuit simulation and analysis streamlined with direct generation of SPICE-compatible RLGC circuit models from layout structures in the IME workflow.
Complex system modeling simplified with support for IBIS-Electrical Module Description (EMD) models, linear buffer models, and automatic Broadband SPICE model extraction.
Signal and memory-interface validation streamlined with transient circuit simulation directly within Serial Link Analysis and support for simultaneous read/write cycle simulations.

For complete details, refer to the What's New documentation for release 26.1 and the accompanying README_CCR.txt file on the Cadence Downloads site.

If you have questions or feedback, send them to pcbbloggers@cadence.com.

To receive release announcements and related information directly in your mailbox, subscribe to the PCB Design blog.

Allegro Release Team

Sigrity and Systems Analysis 2026.1 Release Now Available

2026-10-12T22:15:00Z

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2026.1 release is now available for download at Cadence Downloads. This blog provides quick access to software downloads, documentation, and release resources, and highlights some of the key capabilities and enhancements available in this release.(read more)

Streamlining SI/PI Analysis with Clarity 3D Solver’s New ACE Technology

2026-10-09T04:58:00Z

Today’s complex electronic designs, particularly in the context of high-speed interconnects, 3D-ICs, and advanced packaging, require robust electromagnetic (EM) simulation tools that balance accuracy, speed, and integration. Two new resources are available that introduce the new automated channel extraction (ACE) feature within the Clarity 3D Solver and highlight how the core technical advancements in this innovation address the challenges of large-scale simulation, workflow automation, and seamless integration with leading EDA platforms.

The on-demand Cadence webinar, Transform Your S/PI Analysis with Clarity 3D Solver, demonstrates the capabilities of the ACE technology, while a new product overview, Streamlining SI/PI Analysis with Clarity ACE Technology, available online and as a downloadable PDF, provides technical details of the key features.

ACE Automated Workflow

Clarity ACE technology addresses a critical industry need: the automation of partitioning and channel extraction in large EM designs. Clarity ACE technology represents a significant advancement in EM simulation automation; by automating the partitioning and extraction of complex design channels, the ACE tool streamlines what were previously manual, error-prone processes. With ACE technology, engineers can assign multiple net groups, perform simultaneous cutouts, and serialize or parallelize the entire workflow. This enables rapid reuse and adaptation of simulation setups across multiple design iterations and layouts, greatly reducing setup and post-processing times.

Traditionally, engineers manually select the nets, define partitions, and manage cutouts as individual projects. They then post-process for frequency domain comparisons or masking—a process prone to errors and inefficiency. ACE technology allows users to import layouts, assign net groups, perform cutouts, and serialize or parallelize simulations with minimal manual input. The flow has been compressed significantly, enabling designers to assign multiple net groups and do multiple cutouts all at the same time and serialize or parallelize the entire process. The figure below shows how Clarity ACE provides a single step process rather than manually manipulating different net groups.

In addition, all the data can be reused from design to design. A very quick partitioning of the entire design can be performed and all the different partitions can be visualized before the simulation is run. The solve progress and the results can be viewed through a single interface using Clarity 3D Solver’s benefits and gold-standard accuracy.

Manual sub-modeling is no longer needed, as the software intelligently segments and solves many channels of a larger system. The tool provides re-aggregation by automatically stitching results back together, providing a holistic view of system performance without the manual overhead. Pre- and post-processing is streamlined by automating the signal integrity/power integrity (SI/PI) data workflow around a high-performance solver, significantly reducing time to results.

Instead of just solving the different blocks serially, engineers can select how many different compute resources are available and how many solves and licenses of Clarity 3D Solver can be used at the same time. Simulation progress can be monitored and load and plot results obtained. As can be seen in the figure below, some of the simulations have already been completed as other ones are starting. This enables the designer to solve several or all of the problems simultaneously, depending on the available resources. Also, from this window, results can be loaded and plotted by going to the view results button.

Integration with Design and Analysis Platforms

A key differentiator of Clarity ACE technology is its deep integration with the broader Cadence ecosystem. The Clarity solver is accessible directly within the Virtuoso Layout Suite for IC-centric and module-centric workflows. Multiple fabrics, such as package modules and ICs, can be imported and simulated natively. In addition, through the Allegro X Design Platform engineers can run Clarity-based analysis workflows from the Allegro PCB and package design environment.

Conclusion

Clarity ACE technology is being employed across a range of high-impact applications, including high-speed packaging, module design, interposers, and advanced IC-level simulations. Its automation and integration capabilities have enabled customers to compress design cycles, reduce manual setup, and achieve rapid, repeatable results. The tool is actively used in customer projects.

Clarity 3D Solver and ACE technology represent a new paradigm in 3D EM simulation, combining automation, scalability, and integration to meet the demands of modern electronic design. By reducing manual effort, enabling parallelized workflows, and supporting comprehensive post-processing, these tools empower engineering teams to achieve faster, more accurate results and accelerate innovation.

To learn more about Clarity 3D Solver and ACE technology, visit the Clarity 3D Solver product page, view the webinar on demand here, and read the product brief here.

Showcase Your PCB and Package Design Expertise with Digital Badges

2026-10-06T09:58:00Z

PCB and Package Design engineers are behind many of today's most innovative electronic products. From library development and schematic creation to advanced package design and SI/PI analysis, their expertise drives successful product development....(read more)

BoardSurfers: Getting Started with SKILL in Allegro X: Testing SKILL Scripts

2026-09-23T09:38:00Z

SKILL programming is one of the most powerful ways to extend and automate workflows in Allegro X PCB Editor. Whether you are experimenting with a new automation idea, testing a utility, or validating a newly developed script, knowing how to quickly load and run SKILL files can significantly improve your productivity.

In many environments, SKILL scripts are automatically loaded using the allegro.ilinit file. However, during development, debugging, or testing, manually loading SKILL scripts provides greater flexibility and faster iteration.

This blog focuses on how to run SKILL files without using the allegro.ilinit file, giving you flexible and immediate control over your scripting workflow. You will learn several methods, such as loading SKILL files, extending the SKILL search path, and identifying the command to run a SKILL script in the PCB Editor.

Why Load SKILL Scripts Manually?

Manual loading is particularly useful when:

Testing a newly developed SKILL script.
Validating script behavior before adding it to your initialization file.
Working with temporary or session-based utilities.
Debugging and refining automation scripts.

This approach lets you experiment quickly without modifying your standard environment.

Method 1: Load a SKILL File from the Working Directory

The simplest approach is to place the SKILL file in the same directory as your board file.

Copy the SKILL file into your working directory.
The following image shows an example directory containing a sample board and a SKILL file 251_Constraint_Flow.brd and nopinnets.il.
Launch Allegro X PCB Editor.
Load the SKILL file.
Enter the skill load("nopinnets.il") command in the Command window.

If the script loads successfully, the command line displays t as the final entry.

Method 2: Load a SKILL File Using a Full Path

If the SKILL file is stored outside the working directory, specify its complete path directly.

skill load("C:/work/skill/nopinnets.il")

This method is especially useful for centralized SKILL repositories and shared utility locations.

Method 3: Add a Custom SKILL Path

If you frequently use SKILL files from the same directory, you can add that location to the SKILL search path using the setSkillPath command. This command appends the specified directory to the existing SKILL path. Once added, SKILL files in that directory can be loaded without entering the full path each time.

For example, if you save your SKILL files in C:/work/skill directory, you can use the following command:

setSkillPath(buildString(append1(getSkillPath() "C:/work/skill")))

This approach is ideal when repeatedly testing or developing multiple SKILL utilities.

How to Identify the Command Used by a SKILL File

After loading a SKILL file, you need to know which command to enter in the PCB Editor command window to execute the utility.

A simple way to identify the command is to open the SKILL file in an ASCII text editor and review the developer comments.

Developers often include:

Single-line comments using semicolon (;)
Block comments using /* */

Another useful technique is to locate the axlCmdRegister function, which registers the command name associated with a SKILL script.
For example:

nopinnets is the command entered in PCB Editor.
ashNetsWithNoPins is the SKILL function being executed.

Conclusion

Manually loading SKILL scripts in Allegro X PCB Editor gives you a fast and flexible way to test, debug, and validate automation scripts without modifying your standard startup configuration. Once a script is fully tested, you can add it to the allegro.ilinit file for automatic loading and long-term use.

As you explore further, SKILL becomes a powerful tool that helps you automate repetitive tasks and focus more on design work, making your overall workflow faster and more efficient.

To learn in detail about this course, enroll in the course Allegro X PCB Editor SKILL Programming Language Training on the Cadence ASK portal. Click the Training Bytes link or visit Cadence ASK and search for Free Online Training Bytes (Videos) under the video library.

Want To Level Up Even Faster?

If you want structured learning, pair the Training Bytes with Accelerated Learning, where you can test out of what you already know and focus only on areas that need attention—saving even more time.

Cadence Training Services now offers free Digital Badges for all popular online training courses. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can add the digital badge to your email signature or any social media channels, such as Facebook or LinkedIn, to highlight your expertise.

To find out more, see the blog post Take a Cadence Masterclass and Get a Badge.

You might also be interested in the training Learning Map, which guides you through recommended course flows as well as tool experience and knowledge-level training modules. To find information on how to get an account, visit the Cadence Learning and Support portal.

SUBSCRIBE to the Cadence training newsletter to be updated about upcoming training, webinars, and much more. If you have any questions about courses, schedules, online training, blended/virtual live training, or public or onsite live training, reach out to us at Cadence Training.

Related Training Bytes

Related Blogs

Available on Demand: Tackling the Complexity of Next-Generation IC Packaging

2026-09-19T02:00:00Z

Learn how Cadence is addressing the challenges of complex IC packaging design and view real use-case scenarios in an on-demand webinar presented by the Northeast Microelectronic Coalition (NEMC), a collaborative organization driving innovation in U.S. microelectronics.

The high costs of moving to next-generation silicon nodes and the need to integrate additional high-density memories for AI-based applications are driving designers of system-level IC packages to better understand the impacts between integrated silicon or component blocks. This webinar provides valuable technical insight into system-level design and analysis of next-generation IC packaging using Cadence's in-design analysis (IDA) solutions. Signal integrity, power integrity (SI/PI), and thermal validation with Allegro X Advanced Packaging Designer, Sigrity X, and Clarity 3D Solver are integrated directly into Cadence PCB layout platforms, enabling engineers to obtain a real-time snapshot of the effects of placement and proximity on electrical performance early in the design process. This innovative approach uncovers problems that can be corrected before the final validation stage, cutting up to 50% of design respins.

NEMC offers free membership to those interested in advancing microelectronics. Visit their membership page.

AMBA Over UCIe: Building Coherent Multi-Die Systems

2026-09-11T06:53:00Z

While CHI C2C brings coherence and protocol intelligence to multi-die architectures, it is UCIe that enables these capabilities to scale efficiently in real hardware. UCIe does not just transport CHI traffic, it enhances its performance, reliability, and scalability across chiplet-based systems. (read more)

Using In-Design Analysis to Cut PCB Design Cycles in Half

2026-09-04T05:25:00Z

To succeed in today’s highly competitive electronics markets, designers are moving multiphysics analysis technologies from the validation stage to becoming an integral part of each phase of the design process at the chip, package, board, and complete system level. This in-design analysis (IDA) strategy serves to uncover defects early in the design process/workflow, improving electronic product and system quality while shortening design cycles by catching signal/power-integrity (SI/PI) and thermal issues before they require late-stage rework.

A recent webinar, now available on demand, demonstrates how integrating IDA early in the workflow enables SI, PI, and thermal validation directly within the layout, enabling design teams to cut cycles by as much as 50%. By embedding these checks during the design phase, teams can iterate more rapidly, reduce risks, and shift much of the workload from the traditional "analyze after routing" approach to a more efficient "analyze while designing" methodology. The webinar presents practical workflows through real-world success stories that use Cadence’s Allegro X Design Platform with Sigrity X SI/PI analysis and Clarity 3D Solver platforms to validate signal, power, and thermal aspects of PCB designs. The latest new features that enhance productivity and foster greater team collaboration are highlighted, and a preview of an upcoming deep-dive presentation is given that focuses on the role of key design team members in maximizing the benefits of IDA.

Cadence In-Design Analysis

The Cadence IDA design solution offers automation, integration, and optimization all within a single environment, providing rapid electrical and thermal checks directly inside the layout workspace and enabling engineers to perform what-if scenario modeling that simulates adjustments to traces and components before committing to a final route, as well as multiphysics convergence that connects layout tools smoothly with high-capacity solvers like Sigrity X and the Clarity 3D Solver. This early error detection ability catches impedance, thermal, and voltage drop issues and reduces expensive respins. The figure below shows how the workflow incorporates the Allegro Constraint Manager and Sigrity X Topology Workbench for both pre-layout and post-route analysis.

Allegro X PCB IDA provides layout-based checking and analysis for the entire design team with enhanced analysis workflows that are integrated with fundamental SI/PI analysis flows directly integrated with Sigrity X SI/PI analysis technology. Sigrity X Aurora PCB analysis is fast, actionable, and easy-to-use design screening, SI/PI, and thermal analysis. Directly integrated into the Allegro X PCB design framework, it brings IDA to PCB analysis with overlays that display actionable analysis results through distributed processing and high-performance computing support that enables unparalleled accuracy in a significantly shortened design cycle.

Design Demonstration

The webinar presents a design example of a single-board computer with a dual-core system on chip in the center, 16-core real-time processor on the right, and a gigabyte double-data rate (DDR). The demo concentrates mainly on power-related issues with the double-data rate DDR interface.

Success Stories/Case Studies

The following customer stories are presented following the demonstration.

ZF Automotive: Sigrity X for Automotive PCB Design Efficiency
ZF Automotive, a major global technology company supplying advanced mobility systems for passenger cars, commercial vehicles, and industrial technology, uses Sigrity X to manage signal, power, and thermal concerns before it is too late.
Formfactor, Inc.: Sigrity X for Early Analysis on Massive Test Boards
Sigrity X enables Formfactor, Inc., a provider of test and measurement technologies for integrated circuits, to skip the translation phase, compress design cycles, and obtain results more quickly.
Amkor Technology, Inc.: In-Design Analysis Success
Amkor Technology, a provider of semiconductor packaging and test services, employs the Cadence IDA workflow to bolster its limited staff of SI/PI analysis experts.
Chipletz: Advancing the PCB Design Flow with In-Design Analysis
Chipletz, an advanced packaging technology company that addresses the increasing demand for compute performance by offering denser computing capability, uses Sigrity X as part of its IDA flow to quickly find and fix SI/PI issues during the layout process.

Conclusion

“Using In-Design Analysis to Cut PCB Design Cycles in Half” discusses Cadence’s in-design analysis workflows, which allow designers to integrate SI, PI, and thermal validation directly within the layout, helping design teams to cut cycles by as much as 50%. The analysis of a PCB using the Allegro X Design Platform with Sigrity X SI/PI analysis and Clarity 3D Solver tools is presented, along with several practical workflows that are illustrated with real-world success stories and case studies.

The webinar is available to view on demand here.

Why Does Every Chiplet Supply Chain Need a Chain of Custody?

2026-08-25T14:30:00Z

The race to build larger, more capable AI systems has fundamentally changed semiconductor design. As the industry embraces heterogeneous integration and chiplet-based architecture, performance is no longer the only measure of success. Increasingly, the ability to prove that every component can be trusted throughout its lifecycle is becoming just as critical.

The semiconductor industry has largely solved the engineering challenges of building chiplet-based systems. Now it faces a far more difficult question:

Can every chiplet in that package be trusted—not just at deployment, but throughout its entire journey from design to system assembly?

As AI systems become larger, more modular, and increasingly assembled from chiplets sourced across multiple organizations, security is no longer limited to protecting the finished device. It must extend across every stage of the lifecycle—from RTL design and manufacturing to provisioning, packaging, and final system integration.

Every chiplet moves through multiple organizations before becoming part of a finished system. Every handoff, from design and manufacturing to provisioning, packaging, assembly, and deployment creates another point where system integrity must be preserved. Every one of those transitions is also a potential attack surface.

This is why security can no longer be confined to the chip itself. It must establish an unbroken chain of custody across the entire silicon supply chain, ensuring that every participant can verify the integrity, ownership, and authenticity of the components they receive.

Chiplets Change More than Silicon Architecture

Chiplets promise faster innovation by allowing semiconductor companies to combine best-in-class silicon rather than building increasingly complex monolithic SoCs.

Instead of designing one enormous chip, organizations can assemble specialized compute, memory, I/O, security, and accelerator chiplets into a single package. This modular approach accelerates development, improves manufacturing efficiency, enables greater silicon reuse, and allows products to be scaled by combining standardized building blocks instead of creating multiple monolithic designs.

But the real transformation goes far beyond packaging.

Chiplets fundamentally optimize how semiconductor products are designed, manufactured, and delivered across an ecosystem of companies. This paradigm change opens up new opportunities, as well as new risks.

A single package may include chiplets designed by different engineering teams, manufactured at different foundries, packaged by specialized OSAT providers, provisioned by another manufacturing partner, and ultimately integrated into a complete system by an OEM.

What was once a relatively linear manufacturing flow has evolved into a highly distributed engineering ecosystem.

This shift creates enormous opportunities for innovation, collaboration, and faster time to market. Industry initiatives such as UCIe and the Open Compute Project (OCP) are helping establish standards that make interoperable chiplet ecosystems possible, enabling organizations to mix and match silicon from multiple sources more efficiently.

However, interoperability alone is not enough.

Every organization involved in designing, manufacturing, provisioning, packaging, or assembling a chiplet becomes part and parcel of the product's security story.

As chiplet ecosystems continue to expand, protecting individual chips is no longer sufficient. Security must extend across every participant in the supply chain, making end-to-end assurance just as important as interoperability and performance.

The Greatest Security Risk Lies Beyond the Silicon

When people think about semiconductor security, they often focus on secure boot, firmware integrity, encryption, or runtime attacks. These capabilities remain essential. But many of the most significant compromises occur long before a device is ever powered on.

Every transition in the semiconductor supply chain represents a transfer of ownership.

That includes those exemplary steps:

RTL moving into implementation
Silicon entering manufacturing
Devices leaving the foundry
Firmware being provisioned during manufacturing
Chiplets moving through OSAT assembly
Final systems being delivered to OEMs and customers

Each transition introduces another opportunity for unauthorized modification.

An attacker does not necessarily need to alter the silicon itself.

Compromising provisioning keys, replacing firmware, introducing unauthorized credentials, modifying one-time programmable (OTP) configuration data, or exploiting insecure ownership transfers can permanently undermine the integrity of the final system before it ever reaches the customer.

As chiplet ecosystems become increasingly distributed, these risks multiply. Every additional participant expands the attack surface, making supply chain assurance as important as protecting the silicon itself.

Why Traditional Security is not Enough

Many organizations assume that implementing secure boot or encrypting firmware is sufficient to protect a chiplet-based system.

It isn't.

Security mechanisms added after manufacturing cannot guarantee that the underlying hardware has remained authentic throughout its journey.

If ownership cannot be verified...

If provisioning cannot be authenticated...

If firmware cannot be proven genuine...

...then secure boot begins from an already compromised foundation.

The challenge is no longer simply protecting software.

It is protecting ownership, provenance, and integrity throughout the manufacturing lifecycle. That requires rethinking security as something that begins long before the operating system loads, or even before firmware is installed.

Security Needs a Chain of Custody

The answer is not another isolated security feature. It is an end-to-end chain of custody.

The concept is familiar in industries such as pharmaceuticals, aerospace, and logistics, where every transfer of a high-value asset must be recorded, authenticated, and verified. Chiplet ecosystems now require the same level of assurance, effectively delivered through transparency and auditability.

A chain of custody is far more than manufacturing traceability. It establishes who owns a chiplet at every stage of its lifecycle, who is authorized to provision it, how ownership is securely transferred between organizations, and how unauthorized modifications are prevented. Every transition is cryptographically verified, preserving the integrity established during design through manufacturing, packaging, and deployment.

Without this capability, every ownership transfer becomes a potential opportunity for compromise. With it, each participant inherits cryptographic assurance that the device has remained authentic and uncompromised throughout its journey.

This means every chiplet should leave the factory already protected, not shipped in an open state waiting to be secured later. Instead, security should begin with mechanisms that enable:

Secure ownership transfer
Protected key provisioning
Authenticated firmware installation
Device identity
Secure boot
Cryptographic attestation

Rather than isolated security controls protecting individual stages, every manufacturing step builds upon the integrity established by the previous one. The result is an unbroken chain of assurance from silicon creation to deployed system.

A Framework for Securing Chiplet Systems

One useful way to think about chiplet security is across three complementary layers:

Layer	Purpose
Trusted Supply Chain	Secure manufacturing, ownership transfer, provisioning, and chain of custody.
Trusted Platform	Secure boot, firmware integrity, operating systems, and runtime protection.
Trusted Identity	Device identity, cryptographic attestation, and verifiable provenance throughout the lifecycle.

Each layer depends on the one before it. Without a secure supply chain, higher-level software protections have no trustworthy foundation.

A Hardware Root of Trust Makes the Chain of Custody Possible

A chain of custody is only meaningful if it can be enforced. That is where a hardware root of trust becomes essential.

More than simply another security IP block, it provides the cryptographic foundation that enables organizations to establish provable ownership, authenticate provisioning operations, securely onboard third-party chiplets, and preserve system integrity across every manufacturing stage. In other words, it transforms security policies into enforceable controls.

From the moment a chiplet leaves the fab, the hardware root of trust ensures that it is never in an unsecured default state. Ownership is established from the beginning, and every subsequent transfer can be authenticated before new firmware, configuration data, or manufacturing credentials are introduced.

This foundation enables secure provisioning, authenticated firmware updates, cryptographic identity, secure boot, and device authentication—all while preserving the integrity of the overall system as it moves through multiple organizations.

Most importantly, it allows security to survive every transfer across the manufacturing ecosystem. Rather than re-establishing integrity at each stage, every participant inherits cryptographically verifiable assurance from the previous one, creating an unbroken chain of custody from RTL to the final system.

From Protection to Proof: Why Attestation Matters

For chiplet-based systems, protecting firmware is only part of the story. Increasingly, organizations must also demonstrate that the underlying hardware, including the security components responsible for protecting cryptographic keys, identities, and provisioning mechanisms, has remained authentic throughout manufacturing and deployment.

This is where attestation fundamentally changes the security conversation. Traditional security focuses on preventing attacks. Attestation focuses on proving integrity. Rather than simply claiming that a chiplet is secure, manufacturers can cryptographically demonstrate:

Where the chiplet originated
Who owned it throughout manufacturing
How it was provisioned
Which firmware was installed
Whether critical hardware security components remain authentic
That every stage of manufacturing preserved the integrity of the device

This distinction is becoming increasingly important as semiconductor supply chains grow more distributed. Customers, regulators, hyperscalers, and ecosystem partners increasingly expect organizations not only to implement security controls but also to demonstrate, with verifiable evidence, that those controls remain effective throughout the manufacturing lifecycle.

Attestation transforms security from an internal engineering capability into an externally verifiable assurance. It provides every stakeholder with confidence that the chiplet they receive is the same chiplet that was designed, manufactured, provisioned, and assembled—without unauthorized modification.

In that sense, attestation becomes much more than a technical feature. It becomes the digital passport of the chiplet. Just as a passport documents the identity and journey of an individual, attestation provides cryptographic evidence of a chiplet's provenance, ownership, configuration, and integrity throughout its lifecycle.

For mission-critical markets such as automotive, aerospace, defense, healthcare, and hyperscale AI, that level of assurance is rapidly becoming as valuable as silicon performance itself.

Turning Security into a Competitive Advantage

Security has traditionally been viewed as a cost of doing business, a necessary investment to reduce risk. In the era of chiplets, it can become something much more valuable. Organizations that establish an auditable chain of custody gain benefits that extend well beyond cybersecurity. They can:

Strengthen supply chain assurance across multiple manufacturing partners
Simplify compliance with emerging security and regulatory requirements
Accelerate collaboration across distributed semiconductor ecosystems
Increase customer confidence in mission-critical deployments
Reduce the business risk associated with third-party silicon integration
Differentiate themselves through demonstrable integrity and provenance

As heterogeneous integration becomes mainstream, customers will increasingly expect manufacturers to provide evidence—not simply assurances—that every component entering their systems has maintained its integrity throughout its lifecycle.

In other words, security is evolving from a defensive capability into a business enabler.

Organizations that can prove the authenticity and provenance of their chiplet ecosystems will be better positioned to earn customer confidence, streamline ecosystem collaboration, and meet the growing demands for supply chain transparency.

Enabling Trusted Chiplet Ecosystems

As chiplet ecosystems continue to mature, security cannot be solved by any single company.

It requires industry-wide collaboration across semiconductor vendors, IP providers, foundries, packaging houses, standards organizations, and system integrators.

This is why ecosystem initiatives such as UCIe and the Open Compute Project (OCP) are increasingly incorporating security and manageability into their evolving chiplet frameworks. Interoperability alone is not enough. The industry also needs common approaches to ownership, identity, provisioning, attestation, and lifecycle assurance.

Following the integration of Secure-IC into Cadence, this expertise has become part of Cadence's broader silicon security portfolio. Building on more than a decade of hardware security innovation, Cadence is helping customers embed security throughout the chiplet lifecycle—from architecture and IP integration through manufacturing and deployment.

Rather than treating security as an isolated IP block, Cadence's approach integrates hardware roots of trust, secure provisioning, cryptographic identity, secure boot, and attestation into a broader strategy for enabling trusted chiplet ecosystems. The objective is not simply to protect individual devices. It is to help establish an ecosystem where every participant can securely transfer ownership, verify integrity, and maintain assurance from silicon creation to deployed system.

The Future of Chiplets Depends on Verifiable Trust

The success of chiplets will not be determined solely by bandwidth, packaging technology, or interoperability standards. It will depend on whether every participant in the ecosystem can answer one fundamental question:

Can you prove this chiplet has remained authentic from design to deployment?

As AI infrastructure grows larger and semiconductor supply chains become increasingly distributed, organizations can no longer rely on implicit assumptions about the authenticity and integrity of every component.

They must establish cryptographic assurance that survives every manufacturing stage, every ownership transfer, and every system integration. That is why an end-to-end chain of custody is rapidly evolving from a security best practice into a foundational requirement for chiplet-based systems.

Just as every modern chiplet is expected to deliver higher performance, interoperability, and scalability, it should also provide verifiable integrity, authenticated provenance, and cryptographic evidence of its journey from manufacturing through deployment.

In a modular silicon world, security must be measurable—not assumed. Every chiplet should carry verifiable proof of its authenticity and integrity throughout its lifecycle. Compliance to open standards, such as OCP / FCSA (to which Cadence is a lead contributor) is key in this respect.

Want to learn more? Watch the full conference session by Sylvain GUILLEY, Fellow, Secure-IC R&D, Cadence, explore how a hardware root of trust, secure ownership transfer, and an end-to-end chain of custody help protect chiplet-based systems throughout the supply chain, and how Cadence is advancing secure chiplet ecosystems.

BoardSurfers: Automate PCB Constraints with Allegro X Constraint Compiler

2026-08-19T09:10:00Z

Modern PCB design is becoming increasingly complex, especially when it comes to defining and managing constraints for high-speed designs. Creating constraints manually, reusing constraint rules across designs, and managing complex constraint definiti...

(read more)

Register Now: Tackling the Complexity of Next-Generation IC Packaging

2026-08-12T04:54:00Z

Today’s IC packaging solutions continue to grow in complexity, posing several challenges. Because of the high costs of moving to next-generation silicon nodes and the need to integrate additional high-density memories for AI-based applications, designers of system-level IC packages need to better understand the impacts between integrated silicon or component blocks. Cadence’s in-design analysis (IDA) solutions integrate signal integrity, power integrity (SI/PI), and thermal validation directly into its PCB layout platforms, enabling engineers to obtain a real-time snapshot of the effects of placement and proximity on electrical performance early in the design process. This innovative approach uncovers problems that can be corrected before the final validation stage, cutting up to 50% of design respins.

Register Now

Learn how Cadence is addressing these challenges and view real use-case scenarios in a webinar on August 28 at 11:00 am presented by the Northeast Microelectronic Coalition (NEMC). Mark your calendars and register here to attend this free webinar to gain valuable technical insight into system-level design and analysis of next-generation IC packaging using Cadence tools.

Designing Integrated SOI X-Band Radar Switches with Cadence Workflow

2026-07-28T04:46:00Z

RF systems operate under tight budgets for loss, coupling towards unwanted paths, timing control, and power handling. As the radar and wireless infrastructure market moves toward more complex and higher-performing hardware, RFIC designers face increasing pressure. Transmit/receive (T/R) switches are core elements of time-duplexed RF systems, and must simultaneously meet aggressive requirements on insertion loss, isolation, power handling, and switching speed, while remaining manufacturable at scale. The massive silicon manufacturing ecosystem and the best-in-class RonCoff figure of merit performance rating of silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technologies offer an attractive solution for novel T/R front-end switches. However, the low-voltage device breakdown requires stacked circuit topologies that degrade switching-time performance.

Fabless semiconductor company LintrinsIC Semiconductors Inc. has developed a patented approach to solve the typical tradeoff between power handling and switching time with tailored analog/RF circuit solutions that enable high-power SOI switches to enter the X-band radar market with best-in-class overall metrics. Achieving first-pass success for these types of designs requires an EDA-integrated simulation workflow that encompasses analog domain analysis for the integrated circuit, tightly coupled to package and PCB level electromagnetic (EM) and thermal modeling.

Giuseppe Michetti, CTO of LintrinsIC, presented at CadenceLIVE Silicon Valley 2026 an end-to-end EDA-driven workflow that converges circuit design, EM analysis, thermal modeling, and package/PCB co-design in a Cadence Virtuoso/Clarity 3D Solver/Sigrity X implementation that enables designers to centralize and model chip-level components, as well as packaging and board design.

Technology and Modeling Challenges

The figure below is a simple depiction of how a radar system works. The radar pulse goes through a switch, into an antenna, and then in the air hits a target. As the pulse comes back, if the switch is now in the other position, the pads can be decoded with the time and switch setting information, which can be used to uniquely track the target in space. Focusing on the role of the switch in the system, you can see that the earth path goes through the switch twice. By improving the loss in the switch, system performance increases.

The system needs to be both agile and reconfigurable at the same time, so the switching speed in some scenarios is crucial in determining parameters. To reach targets that are further out in space, more power is needed, so this switch needs to be able to withstand this power without introducing distortion. The switch is at the core of this system, and because of the many requirements, the design is typically over-constrained, and only a few technologies are suitable for this complex design.

Cadence Flow for RF/Thermal Modeling

Using the integration capability of Cadence’s Virtuoso Layout Suite, Clarity 3D Solver, and Sigrity X platforms, a 3D finite-element method (FEM) EM model can be extracted directly from Virtuoso layout data. The same model can be reused for thermal performance estimation and backfitting in the Virtuoso netlist. This approach captures first-order effects that are absent in foundry PDKs, including package-driven isolation degradation, bandwidth limitations, insertion loss underestimation, and temperature-dependent power handling.

The LintrinsIC CadenceLIVE presentation describes this methodology using an LT0001 X-band SOI single-pole double-throw (SPDT) switch in a 4x4 quad flat no-lead (QFN) package. Measured hardware results show strong correlation, demonstrating the effectiveness of an integrated EDA workflow for RF and packaging design.

Conclusion

Design flow optimization is crucial for silicon success in RF, and conventional analog/IC tools are limited in the degree of optimization sophistication they provide. The unique, patented approach LintrinsIC has developed that leverages the Cadence Virtuoso/Clarity/Sigrity workflow solves the typical tradeoff between power handling and switching time and is delivering promising hardware correlations results.

To learn more about this flow and the technology behind it, you can view the presentation on the CadenceLIVE Silicon Valley 2026 on-demand page.

The following design examples are discussed in the presentation.

Design Example #1

Design Example #2

Design Example #3

Design Example #4

Design Example #5

Ascent: Training Insights: Hierarchical Design in Allegro X PCB System Capture

2026-07-23T00:00:00Z

As PCB designs become larger and more complex, flat schematics are harder to manage. As projects grow, the number of schematic pages increases, making it more difficult to trace connectivity and increasing the risk of errors when changes are introduc...(read more)