System, PCB, & Package Design

High-Speed Heterogeneous Integration with Multiphysics Analysis for TSMC SoW-X

2026-07-08T04:30:00Z

2.5D advanced packaging is becoming increasingly critical as the demand for AI and high-performance computing (HPC) applications continues to rise and monolithic die size hits reticle limit. To sustain continuous growth in computing performance, advanced packaging technologies are constantly evolving. TSMC's System-on-Wafer (TSMC-SoW™) technology and its highly advanced design necessitate a reliable and efficient high-performance electromagnetic (EM) analysis tool.

Design Optimization for SerDes Beyond 200G Interconnects and PDNs with Clarity 3D Solver

CadenceLIVE 2026 included a presentation by Cadence customer Global Unichip Corp. (GUC) discussing how GUC uses Clarity 3D Solver and Sigrity X PowerSI analysis technologies to perform signal integrity/power integrity (SI/PI) simulations for high-speed key IP on SoW-X, including serializer/deserializer (SerDes) 212G, GUC's Universal Chiplet Interconnect Express (GUCIe) D2D 64G, and more. An example is provided showing how the Clarity solver is used to analyze the signal integrity of the SerDes 212G signals on SoW-X. Through the visualized EM field provided by the tool, the near-end crosstalk (NEXT) at the micro bump (μBump) and ball-grid array (BGA) interfaces is strengthened from approximately −46dB (failed spec. −65dB) to about −74dB (pass spec.), while the far-end crosstalk (FEXT) is improved from approximately −27dB (failed spec. −40dB) to about −60dB (pass spec.).

S-Parameters Correlation Between Third-Party EDA vs. Clarity 3D Solver

The figure below compares the S-parameters extracted by the Clarity 3D Solver with those from a third-party 3D full-wave solver, showing very similar trends between the two approaches.

The discrepancy in the worst-case SDD21/SDD11 at 53GHz is within approximately 0.6dB, while the difference in NEXT/FEXT at 53GHz is within 0.2dB. Notably, compared to the third-party 3D full-wave solver, Clarity extraction not only provides results similar to those but also achieves about a 15% reduction in runtime when handling scenarios with dozens of SerDes physical layers (PHYs).

SerDes212G PDN Loop Inductance Analysis and Optimization

For the SerDes 212G power delivery network (PDN), GUC designers solved their PDN concerns using Sigrity X PowerSI technology to optimize the loop inductance of the worst-case domain from 337pH, which exceeds the specification limit of 300pH, down to 287pH, bringing it within specification. After optimizing the PDN from the front-side redistribution layer (RDL) to the backside, all five power domains met the constraint of the loop inductance of <300pH, as shown in the figure below.

Conclusion

TSMC's SoW-X is a novel advanced packaging and heterogeneous integration technology that satisfies the demands of HPC and AI applications through the benefits of elevated computing performance, power savings, and area optimization, and more, as well as the tight integration of μBump to BGA, local silicon interconnect (LSI), RDL, PDNs, and voltage regulator modules (VRMs). The optimization strategies (e.g., main route, BGA area, planes, and vias) discussed in this presentation provide insights and guidance for SoW-X design integration.

GUC uses Cadence multiphysics solutions, i.e., 224G-SerDes, UCIe-64GT/s, HBM4, and SoC logic core power rails to successfully meet SI/PI constraints of SerDes above 200G designs. The signal/power integrity analysis in this presentation has been well verified by Cadence's Clarity3D Solver and Sigrity X PowerSI.

To see the full presentation, visit the CadenceLIVE 2026 Silicon Valley on-demand webpage. To learn more about Cadence's tools featured in the GUC presentation, visit the Clarity 3D Solver product webpage and the Sigrity X product webpage.

BoardSurfers: Installation Know-How: Cadence Licensing Floating vs. Single User

2026-07-01T09:11:00Z

In PCB design teams today, the way licenses are managed can have a direct impact on productivity, infrastructure complexity, and how quickly engineers can get started. Floating licenses have been the standard for years, mainly because they allow team...(read more)

BoardSurfers: Getting Started with SKILL in Allegro X: Finding SKILL Scripts

2026-06-25T08:20:00Z

Whether you are new to Allegro X PCB Expert or an experienced layout designer, you may have wondered how SKILL routines are installed and loaded into the tool. SKILL programs are widely used to automate repetitive tasks and improve productivity in PC...(read more)

UCIe Full Signal Integrity Analysis Flow

2026-05-28T06:00:00Z

The increasing complexity and computational demands of 3DHI systems design are challenging. On-package chiplets demand significant simulation and increasing design turns, as more designs are packaging multiple components, which only a few years ago were discretely packaged. The disparate and deep skillsets of these technologies and the exponentially increasing computational demands of newer process nodes threaten to lengthen design times and increase time-to-market ramps.

UCIe Standard

The Universal Chiplet Interconnect Express (UCIe) standard is important for the future of advanced packaging and semiconductor system design. UCIe Full Signal Integrity Analyis with Compliance Check for Heterogenous Integration, presented at the 2026 International Conference & Exhibition on Device Packaging (IMAPS) by Shawn Mills and Ken Willis of Cadence, explores the trends in the industry and overviews Cadence’s complete analysis solutions with UCIe standard compliance checking and verification.

Cadence UCIe Compliance Kit

The Cadence UCIe compliance kit uses a novel approach for signoff verification. This paper details the analysis solution and design architecture with various test cases from Cadence and its customers. The paper includes the following sections: details about the UCIe standard and its importance, heterogeneous integration of the interposer, and lastly, the fine-grained simulations and analysis required to close the design.

The complete paper, recently published in Advancing Microlectronics, is now available to read. More information on Cadence’s UCIe interface can be found in a Cadence webinar case study, How to Sign Off Your UCIe Interface.

Ascent: Training Insights: PCB Design Flow in Allegro X PCB System Capture

2026-05-18T18:30:00Z

Designing modern PCBs requires speed, accuracy, and a seamless transition from concept to layout. However, traditional multi-tool workflows often slow designers down due to disconnected environments, manual documentation, and repetitive validation cy...(read more)

Machine Learning Models for SI/PI Analysis with Meshed Planes

2026-05-13T19:00:00Z

As data rates continue to scale into the multi-tens of gigabits per second, the tolerance for uncertainty in interconnect behavior has significantly diminished. At the same time, packaging and board-level technologies are evolving toward higher density, heterogeneous integration, and greater compliance with standards. These trends have driven widespread adoption of meshed reference planes, including cross-hatch ground planes in flexible and rigid-flex designs (Figure 1), and perforated planes with degassing holes in 3D-IC packages (Figure 2).

An article featured in the April issue of Signal Integrity Journal, "Machine Learning Models for SI/PI Analysis with Meshed Planes" by Cadence"s Jiyue Zhu, Regina Thahir, Xiaoyan Xiong, Gang Kang, and Jian Liu, presents machine learning (ML)-based modeling approaches that efficiently characterize signal integrity (SI) and power integrity (PI) behavior in systems with meshed planes.

Conventional approaches to modeling meshed planes rely on 3D full-wave EM solvers. However, a single metal layer may contain thousands to millions of apertures, making direct simulation computationally expensive and often impractical for iterative design flows. Furthermore, SI and PI effects must often be evaluated simultaneously, further increasing model complexity. The article presents ML-based modeling approaches that efficiently characterize SI and PI behavior in systems with meshed planes.

ANN Architecture and Hyperparameter Optimization

Artificial neural network (ANN) models are developed for pre-layout SI analysis of traces referenced to meshed ground planes. These models offer sufficient flexibility to approximate the nonlinear relationships between meshed-plane geometry and EM response. However, model performance is strongly influenced by hyperparameter selection, including hidden layer count, hidden dimension, learning rate, and training epochs.

Rather than relying on manual tuning or grid search, Gaussian process-based Bayesian optimization is employed to identify optimal ANN hyperparameters.

ML Models for Pre-Layout SI Analysis

To address these challenges, ML models are being introduced as surrogate models for EM-based SI analysis. They focus on traces referenced to meshed ground planes, particularly cross-hatch structures commonly used in flexible and rigid-flex boards. The outputs of the model include per-unit-length inductance and capacitance, single-ended trace impedance, propagation delay, and velocity, differential and common-mode impedance for coupled traces, and differential delay and delay mismatch. These outputs directly support pre-layout SI analysis and constraint definition.

The methods proposed in the article demonstrate high accuracy compared with 3D full-wave EM simulations, while achieving orders-of-magnitude reduction in computation time. The advantages are:

Systematic exploration of the hyperparameter space
Flexible search domains, allowing continuous parameter ranges rather than discretized values
Efficient convergence, achieving improved accuracy with fewer training iterations

Notably, the hidden layer dimensions are not constrained to traditional powers-of-two conventions, enabling more efficient network configurations.

The results suggest that ML-enabled modeling can serve as a practical and scalable solution for SI/PI analysis of complex meshed-plane structures.

Conclusion

Meshed planes are becoming indispensable in modern electronic systems, yet they pose significant challenges for conventional SI and PI analysis methodologies. This article has discussed how ML-based modeling, combined with systematic hyperparameter optimization, offers a practical and accurate alternative to brute-force EM simulation. By enabling fast and reliable prediction of key SI metrics for traces referenced to meshed planes, the proposed approach supports efficient design-space exploration and informed engineering decision-making.

View the complete article and learn more about the Cadence Clarity 3D EM Solver, employed for the analysis of the models discussed in the article.

Mastering Library Development in Allegro X System Capture

2026-04-27T20:30:00Z

Modern schematic-driven design flows rely on accurate, reusable, and well-structured libraries to ensure design correctness, consistency, and smooth downstream PCB implementation. In Cadence's Allegro X System Capture, library development forms the foundation of an efficient design process, enabling seamless schematic creation, constraint application, and PCB implementation.

Join us for this free Cadence technical training webinar with Priyadarshini N D, where we dive into the library development flow in Allegro X System Capture. By adopting best practices, designers can reduce errors, improve collaboration, accelerate schematic creation, and ensure a smooth transition from concept to layout and fabrication.

Agenda:

Creating accurate symbols: Correct pin definitions, electrical types, and visibility
Logical-to-physical mapping: Between schematic symbols and PCB packages
Authoring multiple package symbols: Including single and multiple packages
Creating split symbols: Symmetrical and asymmetrical
Spreadsheet‑based symbol creation for faster and more consistent library development

Date and Time:

Wednesday, May 20

07:00 – 08:00 PDT San Jose / 10:00 – 11:00 EDT New York / 15:00 – 16:00 BST London / 16:00 – 17:00 CEST Berlin / 17:00 – 18:00 IDT Jerusalem / 19:30 – 20:30 IST Bengaluru (Bangalore) / 22:00 – 23:00 CST Beijing

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Debugging RAVEL Rules: From Silent Failures to Visual Proof

2026-04-26T18:40:00Z

Debugging a RAVEL rule can be deceptively difficult. A rule may run without errors, complete successfully, and yet quietly return empty relations or worse, incorrect results. Without debugging cues or a stack trace, these silent failures can stall pr...(read more)

Unlocking High-Speed Serial Link Signal Integrity with AMI Model

2026-04-24T21:30:00Z

As the demand for faster data rates in high-speed interfaces such as PCIe, USB, and DDR continues to escalate, maintaining signal integrity has become a significant challenge for engineers. Traditional SPICE-based simulations, while precise, often su...(read more)

Sigrity and Systems Analysis 2025.1 HF2 Release Now Available

2026-04-22T21:00:00Z

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2025.1 HF2 release is now available for download at Cadence Downloads. This blog contains important links for accessing this release and introduces some of the main features that you can look forward to.(read more)

Streamlining SI/PI Analysis with Clarity 3D Solver’s New ACE Technology

2026-04-03T04:11:00Z

Today’s complex electronic designs, particularly in the context of high-speed interconnects, 3D-ICs, and advanced packaging, require robust electromagnetic (EM) simulation tools that balance accuracy, speed, and integration. Now available on demand, the Cadence TECHTALK, Transform Your S/PI Analysis with Clarity 3D Solver, introduces the new automated channel extraction (ACE) feature within the Clarity 3D Solver and highlights how the core technical advancements in this innovation address the challenges of large-scale simulation, workflow automation, and seamless integration with leading EDA platforms.

ACE Automated Workflow

Clarity ACE technology addresses a critical industry need: the automation of partitioning and channel extraction in large EM designs. Clarity ACE technology represents a significant advancement in EM simulation automation; by automating the partitioning and extraction of complex design channels, the ACE tool streamlines what were previously manual, error-prone processes. With ACE technology, engineers can assign multiple net groups, perform simultaneous cutouts, and serialize or parallelize the entire workflow. This enables rapid reuse and adaptation of simulation setups across multiple design iterations and layouts, greatly reducing setup and post-processing times.

Traditionally, engineers manually select the nets, define partitions, and manage cutouts as individual projects. They then post-process for frequency domain comparisons or masking—a process prone to errors and inefficiency. ACE technology allows users to import layouts, assign net groups, perform cutouts, and serialize or parallelize simulations with minimal manual input. The flow has been compressed significantly, enabling designers to assign multiple net groups and do multiple cutouts all at the same time and serialize or parallelize the entire process. The figure below shows how Clarity ACE provides a single step process rather than manually manipulating different net groups.

In addition, all the data can be reused from design to design. A very quick partitioning of the entire design can be performed and all the different partitions can be visualized before the simulation is run. The solve progress and the results can be viewed through a single interface using Clarity 3D Solver’s benefits and gold-standard accuracy.

Manual sub-modeling is no longer needed, as the software intelligently segments and solves many channels of a larger system. The tool provides re-aggregation by automatically stitching results back together, providing a holistic view of system performance without the manual overhead. Pre- and post-processing is streamlined by automating the signal integrity/power integrity (SI/PI) data workflow around a high-performance solver, significantly reducing time to results.

Instead of just solving the different blocks serially, engineers can select how many different compute resources are available and how many solves and licenses of Clarity 3D Solver can be used at the same time. Simulation progress can be monitored and load and plot results obtained. As can be seen in the figure below, some of the simulations have already been completed as other ones are starting. This enables the designer to solve several or all of the problems simultaneously, depending on the available resources. Also, from this window, results can be loaded and plotted by going to the view results button.

Integration with Design and Analysis Platforms

A key differentiator of Clarity ACE technology is its deep integration with the broader Cadence ecosystem. The Clarity solver is accessible directly within the Virtuoso Layout Suite for IC-centric and module-centric workflows. Multiple fabrics, such as package modules and ICs, can be imported and simulated natively. In addition, through the Allegro X Design Platform engineers can run Clarity-based analysis workflows from the Allegro PCB and package design environment.

Conclusion

Clarity ACE technology is being employed across a range of high-impact applications, including high-speed packaging, module design, interposers, and advanced IC-level simulations. Its automation and integration capabilities have enabled customers to compress design cycles, reduce manual setup, and achieve rapid, repeatable results. The tool is actively used in customer projects.

Clarity 3D Solver and ACE technology represent a new paradigm in 3D EM simulation, combining automation, scalability, and integration to meet the demands of modern electronic design. By reducing manual effort, enabling parallelized workflows, and supporting comprehensive post-processing, these tools empower engineering teams to achieve faster, more accurate results and accelerate innovation.

To learn more about Clarity 3D Solver and ACE technology, view the webinar on demand here.

Online Panel: Chiplets and 3D Heterogenous Integration

2026-03-19T23:00:00Z

Microwave Journal and Signal Integrity Journal recently spearheaded an online panel discussing chiplets and heterogenous integration. Ken Willis, Cadence's senior application engineering group director, multiphysics system analysis, provided his take on the challenges of advanced packaging technologies such as chiplets and 3D heterogenous integration, including integration, stacking, signal integrity, and thermal concerns. He and fellow panel members Chandra Gupta of Remtec and Florian Herrault of PsudolithIC, Inc. examined the simulation, testing, and performance advantages of various approaches to overcoming these challenges.

Key discussion points included the drivers pushing the industry toward chiplet architectures and 3D heterogeneous integration, the most significant electrical challenges to chiplet design, strategies to ensure stable power delivery while minimizing noise, IR drop, and coupling between dies, and how multiphysics co-simulation, including electrical, thermal, and mechanical effects, is helping predict real-world performance.

Ken commented that the biggest change in the design process between traditional semiconductor design and the needs of today's heterogenous integration requirements is the need for system planning to determine how functions are going to be partitioned and placed across multiple physical fabrics.

Through silicon vias (TSVs) and hybrid bonding are some of the many different choices that place the burden on the front-end engineering team to make feasibility and tradeoff choices between these different options to decide on the best implementation path. (Note: Cadence Integrity 3D-IC Platform, Virtuoso Studio, Allegro X APD, Celsius Thermal Solver, Clarity 3D Solver, and Sigrity PowerDC optimize TSV and hybrid bonding designs for HPC and AI applications, ensuring scalability and reliability.)

Ken also noted that power delivery networks (PDNs) for heterogenous systems have become quite complicated and the designer now needs to look beyond the chip design to the entire system from beginning to end because all the different PDN pieces need to be modeled and then simulated together. The challenge is that there are now multiple layouts databases, and solvers and one environment is needed that can take it all the data in and simulate it accurately. (Note: Sigrity X Platform, Clarity 3D Solver, Celsius Thermal Solver, Integrity 3D-IC Platform, Virtuoso Studio, and Allegro X APD provide tools for high-power computing (HPC), AI, and 5G applications that help ensure robust SI/PI in multi-die systems, enabling efficient power delivery and high-speed data transfer.)

Multiphysics co-simulation and how the various effects are modeled together was also discussed. Ken ppointed out that IR drop analysis is now being done across multiple fabrics and it is becoming increasingly important to do that in the context of thermal effects because the heat impacts the IR drop of the PDN. Cadence offers an electro-thermal co-simulation solution to obtain a temperature aware IR drop.

Also becoming more prevalent in the heterogeneous integration space is electromechanical analysis. When designers begin stacking die and have multiple dissimilar materials, thermal stress and warpage become an unknown that must be addressed. (Note: Cadence's multiphysics solutions, including Integrity 3D-IC Platform, Sigrity X Platform, and Clarity 3D Solver are being used to predict and optimize real-world performance in advanced 3D-IC designs, reducing risk and improving reliability.)

View the entire recorded event on demand, including all the discussion points and comments from all the panelists. View our Accelerating Chiplet Integration in heterogenous IC Package Designs on-demand webinar to learn more about a novel new methodology that enables early and iterative optimization of IC package designs. This approach eliminates the need to wait for complete designs or spend excessive time preparing simulations. By integrating in-design analysis and optimization with Cadence's scalable multiphysics analysis engines, IC package engineers can accelerate design cycles and efficiently improve complex package designs.

Cadence's Acquisition of Hexagon D&E: A Game-Changer for Multiphysics Innovation

2026-03-02T21:30:00Z

Having spent six rewarding years at Hexagon Design and Engineering (D&E), followed by the last three years in leadership at Cadence, I have watched both organizations push the boundaries of what is possible in design and engineering. This week's announcement that Cadence has acquired Hexagon's D&E business isn't just a corporate milestone for me personally—it represents a massive leap forward for the entire engineering community.

As products become smarter, smaller, and more complex, the traditional silos between electronic and mechanical design are no longer sustainable. By bringing Hexagon's world-class simulation and analysis portfolio into the Cadence ecosystem, we are providing our customers with a unified pathway to innovation that was previously fragmented.

Bridging the Gap: The Convergence of ECAD and MCAD

For years, the industry has struggled with the "wall" between electronic computer-aided design (ECAD) and mechanical computer-aided design (MCAD). Engineers often found themselves translating data across disparate platforms, leading to versioning errors, delayed timelines, and missed optimization opportunities.

The integration of Hexagon's D&E expertise with Cadence's computational software leadership effectively dissolves this barrier. We are now uniquely positioned to offer a seamless, collaborative workflow. This convergence allows for true electromechanical co-design, where thermal, structural, and electromagnetic constraints are addressed simultaneously rather than sequentially. For our customers, this means faster time to market and the ability to iterate with a level of precision that was previously out of reach.

A Comprehensive Portfolio for the Entire Design Spectrum

The most immediate advantage to our customers is the sheer breadth of the combined portfolio. We are no longer just providing tools; we are providing a complete, end-to-end design and analysis environment. By integrating Hexagon's market-leading structural, acoustic, and manufacturing analysis tools with Cadence's gold-standard electronic design and multiphysics platform, we now cover the entire spectrum:

From Silicon to Systems: We can now analyze how a microscopic chip architecture impacts the structural integrity and thermal performance of a massive industrial system.
Predictive Accuracy: With Hexagon's heritage in high-fidelity simulation and Cadence's strength in algorithmic physics, our customers can now build "digital twins" with unprecedented accuracy, reducing the need for costly physical prototypes.
Optimization at Scale: Whether in aerospace, automotive, or consumer electronics, our combined technologies enable holistic optimization—balancing weight, power consumption, durability, and signal integrity across a single ecosystem.

Driving Value for Our Customers

The ultimate winner in this acquisition is the customer. This union is built on a shared philosophy: empowering engineers to solve the world's most complex challenges.

Our customers will benefit from a unified support structure, a more aggressive R&D roadmap, and a simplified vendor landscape. More importantly, they gain access to a visionary technology stack that is ready for the era of AI-driven design. We are providing the tools to ensure that the next generation of products is not only functional but optimized for a sustainable and hyper-connected world.

A Personal Note on the Journey Ahead

Having walked the halls of both Hexagon and Cadence, I know the talent, passion, and brilliance that exist within both teams. Bringing these two cultures together creates an innovation powerhouse. I am incredibly proud to be part of this journey and look forward to helping our customers leverage this expanded portfolio to turn their most ambitious ideas into reality—the gap between "what is imagined" and "what is engineered" just got significantly smaller.

Learn more about Cadence's acquisition of Hexagon's Design and Engineering Business.

Ascent: Migrate DE-HDL & OrCAD X Capture to Allegro X PCB System Capture

2026-02-26T13:38:00Z

The electronics design world is moving fast, and teams are starting to feel the limits of their existing schematic workflows with Allegro X Design Entry HDL (DE-HDL) or OrCAD X Capture. As design complexity increases and product cycles shrink, engine...(read more)

A Journey Through 2025: PCB and Package Design Learning in Motion

2026-02-12T04:21:00Z

2025 was a year of innovation and learning for PCB and Package Design, with 17 new blogs, expanded training programs, digital badges, accelerated learning options, and smarter tools like the GenAI-powered ASK assistant—empowering engineers to design faster, smarter, and with confidence.(read more)