System, PCB, & Package Design

AMBA Over UCIe: Building Coherent Multi-Die Systems

Nagendra Varma — Fri, 11 Sep 2026 06:53:00 GMT

While CHI C2C brings coherence and protocol intelligence to multi-die architectures, it is UCIe that enables these capabilities to scale efficiently in real hardware. UCIe does not just transport CHI traffic, it enhances its performance, reliability, and scalability across chiplet-based systems. (read more)

Using In-Design Analysis to Cut PCB Design Cycles in Half

MSATeam — Fri, 04 Sep 2026 05:25:00 GMT

To succeed in today’s highly competitive electronics markets, designers are moving multiphysics analysis technologies from the validation stage to becoming an integral part of each phase of the design process at the chip, package, board, and complete system level. This in-design analysis (IDA) strategy serves to uncover defects early in the design process/workflow, improving electronic product and system quality while shortening design cycles by catching signal/power-integrity (SI/PI) and thermal issues before they require late-stage rework.

A recent webinar, now available on demand, demonstrates how integrating IDA early in the workflow enables SI, PI, and thermal validation directly within the layout, enabling design teams to cut cycles by as much as 50%. By embedding these checks during the design phase, teams can iterate more rapidly, reduce risks, and shift much of the workload from the traditional "analyze after routing" approach to a more efficient "analyze while designing" methodology. The webinar presents practical workflows through real-world success stories that use Cadence’s Allegro X Design Platform with Sigrity X SI/PI analysis and Clarity 3D Solver platforms to validate signal, power, and thermal aspects of PCB designs. The latest new features that enhance productivity and foster greater team collaboration are highlighted, and a preview of an upcoming deep-dive presentation is given that focuses on the role of key design team members in maximizing the benefits of IDA.

Cadence In-Design Analysis

The Cadence IDA design solution offers automation, integration, and optimization all within a single environment, providing rapid electrical and thermal checks directly inside the layout workspace and enabling engineers to perform what-if scenario modeling that simulates adjustments to traces and components before committing to a final route, as well as multiphysics convergence that connects layout tools smoothly with high-capacity solvers like Sigrity X and the Clarity 3D Solver. This early error detection ability catches impedance, thermal, and voltage drop issues and reduces expensive respins. The figure below shows how the workflow incorporates the Allegro Constraint Manager and Sigrity X Topology Workbench for both pre-layout and post-route analysis.

Allegro X PCB IDA provides layout-based checking and analysis for the entire design team with enhanced analysis workflows that are integrated with fundamental SI/PI analysis flows directly integrated with Sigrity X SI/PI analysis technology. Sigrity X Aurora PCB analysis is fast, actionable, and easy-to-use design screening, SI/PI, and thermal analysis. Directly integrated into the Allegro X PCB design framework, it brings IDA to PCB analysis with overlays that display actionable analysis results through distributed processing and high-performance computing support that enables unparalleled accuracy in a significantly shortened design cycle.

Design Demonstration

The webinar presents a design example of a single-board computer with a dual-core system on chip in the center, 16-core real-time processor on the right, and a gigabyte double-data rate (DDR). The demo concentrates mainly on power-related issues with the double-data rate DDR interface.

Success Stories/Case Studies

The following customer stories are presented following the demonstration.

ZF Automotive: Sigrity X for Automotive PCB Design Efficiency
ZF Automotive, a major global technology company supplying advanced mobility systems for passenger cars, commercial vehicles, and industrial technology, uses Sigrity X to manage signal, power, and thermal concerns before it is too late.
Formfactor, Inc.: Sigrity X for Early Analysis on Massive Test Boards
Sigrity X enables Formfactor, Inc., a provider of test and measurement technologies for integrated circuits, to skip the translation phase, compress design cycles, and obtain results more quickly.
Amkor Technology, Inc.: In-Design Analysis Success
Amkor Technology, a provider of semiconductor packaging and test services, employs the Cadence IDA workflow to bolster its limited staff of SI/PI analysis experts.
Chipletz: Advancing the PCB Design Flow with In-Design Analysis
Chipletz, an advanced packaging technology company that addresses the increasing demand for compute performance by offering denser computing capability, uses Sigrity X as part of its IDA flow to quickly find and fix SI/PI issues during the layout process.

Conclusion

“Using In-Design Analysis to Cut PCB Design Cycles in Half” discusses Cadence’s in-design analysis workflows, which allow designers to integrate SI, PI, and thermal validation directly within the layout, helping design teams to cut cycles by as much as 50%. The analysis of a PCB using the Allegro X Design Platform with Sigrity X SI/PI analysis and Clarity 3D Solver tools is presented, along with several practical workflows that are illustrated with real-world success stories and case studies.

The webinar is available to view on demand here.

Why Does Every Chiplet Supply Chain Need a Chain of Custody?

Reela Samuel — Tue, 25 Aug 2026 14:30:00 GMT

The race to build larger, more capable AI systems has fundamentally changed semiconductor design. As the industry embraces heterogeneous integration and chiplet-based architecture, performance is no longer the only measure of success. Increasingly, the ability to prove that every component can be trusted throughout its lifecycle is becoming just as critical.

The semiconductor industry has largely solved the engineering challenges of building chiplet-based systems. Now it faces a far more difficult question:

Can every chiplet in that package be trusted—not just at deployment, but throughout its entire journey from design to system assembly?

As AI systems become larger, more modular, and increasingly assembled from chiplets sourced across multiple organizations, security is no longer limited to protecting the finished device. It must extend across every stage of the lifecycle—from RTL design and manufacturing to provisioning, packaging, and final system integration.

Every chiplet moves through multiple organizations before becoming part of a finished system. Every handoff, from design and manufacturing to provisioning, packaging, assembly, and deployment creates another point where system integrity must be preserved. Every one of those transitions is also a potential attack surface.

This is why security can no longer be confined to the chip itself. It must establish an unbroken chain of custody across the entire silicon supply chain, ensuring that every participant can verify the integrity, ownership, and authenticity of the components they receive.

Chiplets Change More than Silicon Architecture

Chiplets promise faster innovation by allowing semiconductor companies to combine best-in-class silicon rather than building increasingly complex monolithic SoCs.

Instead of designing one enormous chip, organizations can assemble specialized compute, memory, I/O, security, and accelerator chiplets into a single package. This modular approach accelerates development, improves manufacturing efficiency, enables greater silicon reuse, and allows products to be scaled by combining standardized building blocks instead of creating multiple monolithic designs.

But the real transformation goes far beyond packaging.

Chiplets fundamentally optimize how semiconductor products are designed, manufactured, and delivered across an ecosystem of companies. This paradigm change opens up new opportunities, as well as new risks.

A single package may include chiplets designed by different engineering teams, manufactured at different foundries, packaged by specialized OSAT providers, provisioned by another manufacturing partner, and ultimately integrated into a complete system by an OEM.

What was once a relatively linear manufacturing flow has evolved into a highly distributed engineering ecosystem.

This shift creates enormous opportunities for innovation, collaboration, and faster time to market. Industry initiatives such as UCIe and the Open Compute Project (OCP) are helping establish standards that make interoperable chiplet ecosystems possible, enabling organizations to mix and match silicon from multiple sources more efficiently.

However, interoperability alone is not enough.

Every organization involved in designing, manufacturing, provisioning, packaging, or assembling a chiplet becomes part and parcel of the product's security story.

As chiplet ecosystems continue to expand, protecting individual chips is no longer sufficient. Security must extend across every participant in the supply chain, making end-to-end assurance just as important as interoperability and performance.

The Greatest Security Risk Lies Beyond the Silicon

When people think about semiconductor security, they often focus on secure boot, firmware integrity, encryption, or runtime attacks. These capabilities remain essential. But many of the most significant compromises occur long before a device is ever powered on.

Every transition in the semiconductor supply chain represents a transfer of ownership.

That includes those exemplary steps:

RTL moving into implementation
Silicon entering manufacturing
Devices leaving the foundry
Firmware being provisioned during manufacturing
Chiplets moving through OSAT assembly
Final systems being delivered to OEMs and customers

Each transition introduces another opportunity for unauthorized modification.

An attacker does not necessarily need to alter the silicon itself.

Compromising provisioning keys, replacing firmware, introducing unauthorized credentials, modifying one-time programmable (OTP) configuration data, or exploiting insecure ownership transfers can permanently undermine the integrity of the final system before it ever reaches the customer.

As chiplet ecosystems become increasingly distributed, these risks multiply. Every additional participant expands the attack surface, making supply chain assurance as important as protecting the silicon itself.

Why Traditional Security is not Enough

Many organizations assume that implementing secure boot or encrypting firmware is sufficient to protect a chiplet-based system.

It isn't.

Security mechanisms added after manufacturing cannot guarantee that the underlying hardware has remained authentic throughout its journey.

If ownership cannot be verified...

If provisioning cannot be authenticated...

If firmware cannot be proven genuine...

...then secure boot begins from an already compromised foundation.

The challenge is no longer simply protecting software.

It is protecting ownership, provenance, and integrity throughout the manufacturing lifecycle. That requires rethinking security as something that begins long before the operating system loads, or even before firmware is installed.

Security Needs a Chain of Custody

The answer is not another isolated security feature. It is an end-to-end chain of custody.

The concept is familiar in industries such as pharmaceuticals, aerospace, and logistics, where every transfer of a high-value asset must be recorded, authenticated, and verified. Chiplet ecosystems now require the same level of assurance, effectively delivered through transparency and auditability.

A chain of custody is far more than manufacturing traceability. It establishes who owns a chiplet at every stage of its lifecycle, who is authorized to provision it, how ownership is securely transferred between organizations, and how unauthorized modifications are prevented. Every transition is cryptographically verified, preserving the integrity established during design through manufacturing, packaging, and deployment.

Without this capability, every ownership transfer becomes a potential opportunity for compromise. With it, each participant inherits cryptographic assurance that the device has remained authentic and uncompromised throughout its journey.

This means every chiplet should leave the factory already protected, not shipped in an open state waiting to be secured later. Instead, security should begin with mechanisms that enable:

Secure ownership transfer
Protected key provisioning
Authenticated firmware installation
Device identity
Secure boot
Cryptographic attestation

Rather than isolated security controls protecting individual stages, every manufacturing step builds upon the integrity established by the previous one. The result is an unbroken chain of assurance from silicon creation to deployed system.

A Framework for Securing Chiplet Systems

One useful way to think about chiplet security is across three complementary layers:

Layer	Purpose
Trusted Supply Chain	Secure manufacturing, ownership transfer, provisioning, and chain of custody.
Trusted Platform	Secure boot, firmware integrity, operating systems, and runtime protection.
Trusted Identity	Device identity, cryptographic attestation, and verifiable provenance throughout the lifecycle.

Each layer depends on the one before it. Without a secure supply chain, higher-level software protections have no trustworthy foundation.

A Hardware Root of Trust Makes the Chain of Custody Possible

A chain of custody is only meaningful if it can be enforced. That is where a hardware root of trust becomes essential.

More than simply another security IP block, it provides the cryptographic foundation that enables organizations to establish provable ownership, authenticate provisioning operations, securely onboard third-party chiplets, and preserve system integrity across every manufacturing stage. In other words, it transforms security policies into enforceable controls.

From the moment a chiplet leaves the fab, the hardware root of trust ensures that it is never in an unsecured default state. Ownership is established from the beginning, and every subsequent transfer can be authenticated before new firmware, configuration data, or manufacturing credentials are introduced.

This foundation enables secure provisioning, authenticated firmware updates, cryptographic identity, secure boot, and device authentication—all while preserving the integrity of the overall system as it moves through multiple organizations.

Most importantly, it allows security to survive every transfer across the manufacturing ecosystem. Rather than re-establishing integrity at each stage, every participant inherits cryptographically verifiable assurance from the previous one, creating an unbroken chain of custody from RTL to the final system.

From Protection to Proof: Why Attestation Matters

For chiplet-based systems, protecting firmware is only part of the story. Increasingly, organizations must also demonstrate that the underlying hardware, including the security components responsible for protecting cryptographic keys, identities, and provisioning mechanisms, has remained authentic throughout manufacturing and deployment.

This is where attestation fundamentally changes the security conversation. Traditional security focuses on preventing attacks. Attestation focuses on proving integrity. Rather than simply claiming that a chiplet is secure, manufacturers can cryptographically demonstrate:

Where the chiplet originated
Who owned it throughout manufacturing
How it was provisioned
Which firmware was installed
Whether critical hardware security components remain authentic
That every stage of manufacturing preserved the integrity of the device

This distinction is becoming increasingly important as semiconductor supply chains grow more distributed. Customers, regulators, hyperscalers, and ecosystem partners increasingly expect organizations not only to implement security controls but also to demonstrate, with verifiable evidence, that those controls remain effective throughout the manufacturing lifecycle.

Attestation transforms security from an internal engineering capability into an externally verifiable assurance. It provides every stakeholder with confidence that the chiplet they receive is the same chiplet that was designed, manufactured, provisioned, and assembled—without unauthorized modification.

In that sense, attestation becomes much more than a technical feature. It becomes the digital passport of the chiplet. Just as a passport documents the identity and journey of an individual, attestation provides cryptographic evidence of a chiplet's provenance, ownership, configuration, and integrity throughout its lifecycle.

For mission-critical markets such as automotive, aerospace, defense, healthcare, and hyperscale AI, that level of assurance is rapidly becoming as valuable as silicon performance itself.

Turning Security into a Competitive Advantage

Security has traditionally been viewed as a cost of doing business, a necessary investment to reduce risk. In the era of chiplets, it can become something much more valuable. Organizations that establish an auditable chain of custody gain benefits that extend well beyond cybersecurity. They can:

Strengthen supply chain assurance across multiple manufacturing partners
Simplify compliance with emerging security and regulatory requirements
Accelerate collaboration across distributed semiconductor ecosystems
Increase customer confidence in mission-critical deployments
Reduce the business risk associated with third-party silicon integration
Differentiate themselves through demonstrable integrity and provenance

As heterogeneous integration becomes mainstream, customers will increasingly expect manufacturers to provide evidence—not simply assurances—that every component entering their systems has maintained its integrity throughout its lifecycle.

In other words, security is evolving from a defensive capability into a business enabler.

Organizations that can prove the authenticity and provenance of their chiplet ecosystems will be better positioned to earn customer confidence, streamline ecosystem collaboration, and meet the growing demands for supply chain transparency.

Enabling Trusted Chiplet Ecosystems

As chiplet ecosystems continue to mature, security cannot be solved by any single company.

It requires industry-wide collaboration across semiconductor vendors, IP providers, foundries, packaging houses, standards organizations, and system integrators.

This is why ecosystem initiatives such as UCIe and the Open Compute Project (OCP) are increasingly incorporating security and manageability into their evolving chiplet frameworks. Interoperability alone is not enough. The industry also needs common approaches to ownership, identity, provisioning, attestation, and lifecycle assurance.

Following the integration of Secure-IC into Cadence, this expertise has become part of Cadence's broader silicon security portfolio. Building on more than a decade of hardware security innovation, Cadence is helping customers embed security throughout the chiplet lifecycle—from architecture and IP integration through manufacturing and deployment.

Rather than treating security as an isolated IP block, Cadence's approach integrates hardware roots of trust, secure provisioning, cryptographic identity, secure boot, and attestation into a broader strategy for enabling trusted chiplet ecosystems. The objective is not simply to protect individual devices. It is to help establish an ecosystem where every participant can securely transfer ownership, verify integrity, and maintain assurance from silicon creation to deployed system.

The Future of Chiplets Depends on Verifiable Trust

The success of chiplets will not be determined solely by bandwidth, packaging technology, or interoperability standards. It will depend on whether every participant in the ecosystem can answer one fundamental question:

Can you prove this chiplet has remained authentic from design to deployment?

As AI infrastructure grows larger and semiconductor supply chains become increasingly distributed, organizations can no longer rely on implicit assumptions about the authenticity and integrity of every component.

They must establish cryptographic assurance that survives every manufacturing stage, every ownership transfer, and every system integration. That is why an end-to-end chain of custody is rapidly evolving from a security best practice into a foundational requirement for chiplet-based systems.

Just as every modern chiplet is expected to deliver higher performance, interoperability, and scalability, it should also provide verifiable integrity, authenticated provenance, and cryptographic evidence of its journey from manufacturing through deployment.

In a modular silicon world, security must be measurable—not assumed. Every chiplet should carry verifiable proof of its authenticity and integrity throughout its lifecycle. Compliance to open standards, such as OCP / FCSA (to which Cadence is a lead contributor) is key in this respect.

Want to learn more? Watch the full conference session by Sylvain GUILLEY, Fellow, Secure-IC R&D, Cadence, explore how a hardware root of trust, secure ownership transfer, and an end-to-end chain of custody help protect chiplet-based systems throughout the supply chain, and how Cadence is advancing secure chiplet ecosystems.

BoardSurfers: Automate PCB Constraints with Allegro X Constraint Compiler

anandd — Wed, 19 Aug 2026 09:10:00 GMT

Modern PCB design is becoming increasingly complex, especially when it comes to defining and managing constraints for high-speed designs. Creating constraints manually, reusing constraint rules across designs, and managing complex constraint definiti...

(read more)

Register Now: Tackling the Complexity of Next-Generation IC Packaging

MSATeam — Wed, 12 Aug 2026 04:54:00 GMT

Today’s IC packaging solutions continue to grow in complexity, posing several challenges. Because of the high costs of moving to next-generation silicon nodes and the need to integrate additional high-density memories for AI-based applications, designers of system-level IC packages need to better understand the impacts between integrated silicon or component blocks. Cadence’s in-design analysis (IDA) solutions integrate signal integrity, power integrity (SI/PI), and thermal validation directly into its PCB layout platforms, enabling engineers to obtain a real-time snapshot of the effects of placement and proximity on electrical performance early in the design process. This innovative approach uncovers problems that can be corrected before the final validation stage, cutting up to 50% of design respins.

Register Now

Learn how Cadence is addressing these challenges and view real use-case scenarios in a webinar on August 28 at 11:00 am presented by the Northeast Microelectronic Coalition (NEMC). Mark your calendars and register here to attend this free webinar to gain valuable technical insight into system-level design and analysis of next-generation IC packaging using Cadence tools.

Designing Integrated SOI X-Band Radar Switches with Cadence Workflow

MSATeam — Tue, 28 Jul 2026 04:46:00 GMT

RF systems operate under tight budgets for loss, coupling towards unwanted paths, timing control, and power handling. As the radar and wireless infrastructure market moves toward more complex and higher-performing hardware, RFIC designers face increasing pressure. Transmit/receive (T/R) switches are core elements of time-duplexed RF systems, and must simultaneously meet aggressive requirements on insertion loss, isolation, power handling, and switching speed, while remaining manufacturable at scale. The massive silicon manufacturing ecosystem and the best-in-class RonCoff figure of merit performance rating of silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technologies offer an attractive solution for novel T/R front-end switches. However, the low-voltage device breakdown requires stacked circuit topologies that degrade switching-time performance.

Fabless semiconductor company LintrinsIC Semiconductors Inc. has developed a patented approach to solve the typical tradeoff between power handling and switching time with tailored analog/RF circuit solutions that enable high-power SOI switches to enter the X-band radar market with best-in-class overall metrics. Achieving first-pass success for these types of designs requires an EDA-integrated simulation workflow that encompasses analog domain analysis for the integrated circuit, tightly coupled to package and PCB level electromagnetic (EM) and thermal modeling.

Giuseppe Michetti, CTO of LintrinsIC, presented at CadenceLIVE Silicon Valley 2026 an end-to-end EDA-driven workflow that converges circuit design, EM analysis, thermal modeling, and package/PCB co-design in a Cadence Virtuoso/Clarity 3D Solver/Sigrity X implementation that enables designers to centralize and model chip-level components, as well as packaging and board design.

Technology and Modeling Challenges

The figure below is a simple depiction of how a radar system works. The radar pulse goes through a switch, into an antenna, and then in the air hits a target. As the pulse comes back, if the switch is now in the other position, the pads can be decoded with the time and switch setting information, which can be used to uniquely track the target in space. Focusing on the role of the switch in the system, you can see that the earth path goes through the switch twice. By improving the loss in the switch, system performance increases.

The system needs to be both agile and reconfigurable at the same time, so the switching speed in some scenarios is crucial in determining parameters. To reach targets that are further out in space, more power is needed, so this switch needs to be able to withstand this power without introducing distortion. The switch is at the core of this system, and because of the many requirements, the design is typically over-constrained, and only a few technologies are suitable for this complex design.

Cadence Flow for RF/Thermal Modeling

Using the integration capability of Cadence’s Virtuoso Layout Suite, Clarity 3D Solver, and Sigrity X platforms, a 3D finite-element method (FEM) EM model can be extracted directly from Virtuoso layout data. The same model can be reused for thermal performance estimation and backfitting in the Virtuoso netlist. This approach captures first-order effects that are absent in foundry PDKs, including package-driven isolation degradation, bandwidth limitations, insertion loss underestimation, and temperature-dependent power handling.

The LintrinsIC CadenceLIVE presentation describes this methodology using an LT0001 X-band SOI single-pole double-throw (SPDT) switch in a 4x4 quad flat no-lead (QFN) package. Measured hardware results show strong correlation, demonstrating the effectiveness of an integrated EDA workflow for RF and packaging design.

Conclusion

Design flow optimization is crucial for silicon success in RF, and conventional analog/IC tools are limited in the degree of optimization sophistication they provide. The unique, patented approach LintrinsIC has developed that leverages the Cadence Virtuoso/Clarity/Sigrity workflow solves the typical tradeoff between power handling and switching time and is delivering promising hardware correlations results.

To learn more about this flow and the technology behind it, you can view the presentation on the CadenceLIVE Silicon Valley 2026 on-demand page.

The following design examples are discussed in the presentation.

Design Example #1

Design Example #2

Design Example #3

Design Example #4

Design Example #5

Ascent: Training Insights: Hierarchical Design in Allegro X PCB System Capture

AsadMakandar — Thu, 23 Jul 2026 00:00:00 GMT

As PCB designs become larger and more complex, flat schematics are harder to manage. As projects grow, the number of schematic pages increases, making it more difficult to trace connectivity and increasing the risk of errors when changes are introduc...(read more)

High-Speed Heterogeneous Integration with Multiphysics Analysis for TSMC SoW-X

MSATeam — Wed, 08 Jul 2026 04:30:00 GMT

2.5D advanced packaging is becoming increasingly critical as the demand for AI and high-performance computing (HPC) applications continues to rise and monolithic die size hits reticle limit. To sustain continuous growth in computing performance, advanced packaging technologies are constantly evolving. TSMC's System-on-Wafer (TSMC-SoW™) technology and its highly advanced design necessitate a reliable and efficient high-performance electromagnetic (EM) analysis tool.

Design Optimization for SerDes Beyond 200G Interconnects and PDNs with Clarity 3D Solver

CadenceLIVE 2026 included a presentation by Cadence customer Global Unichip Corp. (GUC) discussing how GUC uses Clarity 3D Solver and Sigrity X PowerSI analysis technologies to perform signal integrity/power integrity (SI/PI) simulations for high-speed key IP on SoW-X, including serializer/deserializer (SerDes) 212G, GUC's Universal Chiplet Interconnect Express (GUCIe) D2D 64G, and more. An example is provided showing how the Clarity solver is used to analyze the signal integrity of the SerDes 212G signals on SoW-X. Through the visualized EM field provided by the tool, the near-end crosstalk (NEXT) at the micro bump (μBump) and ball-grid array (BGA) interfaces is strengthened from approximately −46dB (failed spec. −65dB) to about −74dB (pass spec.), while the far-end crosstalk (FEXT) is improved from approximately −27dB (failed spec. −40dB) to about −60dB (pass spec.).

S-Parameters Correlation Between Third-Party EDA vs. Clarity 3D Solver

The figure below compares the S-parameters extracted by the Clarity 3D Solver with those from a third-party 3D full-wave solver, showing very similar trends between the two approaches.

The discrepancy in the worst-case SDD21/SDD11 at 53GHz is within approximately 0.6dB, while the difference in NEXT/FEXT at 53GHz is within 0.2dB. Notably, compared to the third-party 3D full-wave solver, Clarity extraction not only provides results similar to those but also achieves about a 15% reduction in runtime when handling scenarios with dozens of SerDes physical layers (PHYs).

SerDes212G PDN Loop Inductance Analysis and Optimization

For the SerDes 212G power delivery network (PDN), GUC designers solved their PDN concerns using Sigrity X PowerSI technology to optimize the loop inductance of the worst-case domain from 337pH, which exceeds the specification limit of 300pH, down to 287pH, bringing it within specification. After optimizing the PDN from the front-side redistribution layer (RDL) to the backside, all five power domains met the constraint of the loop inductance of <300pH, as shown in the figure below.

Conclusion

TSMC's SoW-X is a novel advanced packaging and heterogeneous integration technology that satisfies the demands of HPC and AI applications through the benefits of elevated computing performance, power savings, and area optimization, and more, as well as the tight integration of μBump to BGA, local silicon interconnect (LSI), RDL, PDNs, and voltage regulator modules (VRMs). The optimization strategies (e.g., main route, BGA area, planes, and vias) discussed in this presentation provide insights and guidance for SoW-X design integration.

GUC uses Cadence multiphysics solutions, i.e., 224G-SerDes, UCIe-64GT/s, HBM4, and SoC logic core power rails to successfully meet SI/PI constraints of SerDes above 200G designs. The signal/power integrity analysis in this presentation has been well verified by Cadence's Clarity3D Solver and Sigrity X PowerSI.

To see the full presentation, visit the CadenceLIVE 2026 Silicon Valley on-demand webpage. To learn more about Cadence's tools featured in the GUC presentation, visit the Clarity 3D Solver product webpage and the Sigrity X product webpage.

BoardSurfers: Installation Know-How: Cadence Licensing Floating vs. Single User

Shikha Jain — Wed, 01 Jul 2026 09:11:00 GMT

In PCB design teams today, the way licenses are managed can have a direct impact on productivity, infrastructure complexity, and how quickly engineers can get started. Floating licenses have been the standard for years, mainly because they allow team...(read more)

BoardSurfers: Getting Started with SKILL in Allegro X: Finding SKILL Scripts

anandd — Thu, 25 Jun 2026 08:20:00 GMT

Whether you are new to Allegro X PCB Expert or an experienced layout designer, you may have wondered how SKILL routines are installed and loaded into the tool. SKILL programs are widely used to automate repetitive tasks and improve productivity in PC...(read more)

UCIe Full Signal Integrity Analysis Flow

MSATeam — Thu, 28 May 2026 06:00:00 GMT

The increasing complexity and computational demands of 3DHI systems design are challenging. On-package chiplets demand significant simulation and increasing design turns, as more designs are packaging multiple components, which only a few years ago were discretely packaged. The disparate and deep skillsets of these technologies and the exponentially increasing computational demands of newer process nodes threaten to lengthen design times and increase time-to-market ramps.

UCIe Standard

The Universal Chiplet Interconnect Express (UCIe) standard is important for the future of advanced packaging and semiconductor system design. UCIe Full Signal Integrity Analyis with Compliance Check for Heterogenous Integration, presented at the 2026 International Conference & Exhibition on Device Packaging (IMAPS) by Shawn Mills and Ken Willis of Cadence, explores the trends in the industry and overviews Cadence’s complete analysis solutions with UCIe standard compliance checking and verification.

Cadence UCIe Compliance Kit

The Cadence UCIe compliance kit uses a novel approach for signoff verification. This paper details the analysis solution and design architecture with various test cases from Cadence and its customers. The paper includes the following sections: details about the UCIe standard and its importance, heterogeneous integration of the interposer, and lastly, the fine-grained simulations and analysis required to close the design.

The complete paper, recently published in Advancing Microlectronics, is now available to read. More information on Cadence’s UCIe interface can be found in a Cadence webinar case study, How to Sign Off Your UCIe Interface.

Ascent: Training Insights: PCB Design Flow in Allegro X PCB System Capture

AsadMakandar — Mon, 18 May 2026 18:30:00 GMT

Designing modern PCBs requires speed, accuracy, and a seamless transition from concept to layout. However, traditional multi-tool workflows often slow designers down due to disconnected environments, manual documentation, and repetitive validation cy...(read more)

Machine Learning Models for SI/PI Analysis with Meshed Planes

MSATeam — Wed, 13 May 2026 19:00:00 GMT

As data rates continue to scale into the multi-tens of gigabits per second, the tolerance for uncertainty in interconnect behavior has significantly diminished. At the same time, packaging and board-level technologies are evolving toward higher density, heterogeneous integration, and greater compliance with standards. These trends have driven widespread adoption of meshed reference planes, including cross-hatch ground planes in flexible and rigid-flex designs (Figure 1), and perforated planes with degassing holes in 3D-IC packages (Figure 2).

An article featured in the April issue of Signal Integrity Journal, "Machine Learning Models for SI/PI Analysis with Meshed Planes" by Cadence"s Jiyue Zhu, Regina Thahir, Xiaoyan Xiong, Gang Kang, and Jian Liu, presents machine learning (ML)-based modeling approaches that efficiently characterize signal integrity (SI) and power integrity (PI) behavior in systems with meshed planes.

Conventional approaches to modeling meshed planes rely on 3D full-wave EM solvers. However, a single metal layer may contain thousands to millions of apertures, making direct simulation computationally expensive and often impractical for iterative design flows. Furthermore, SI and PI effects must often be evaluated simultaneously, further increasing model complexity. The article presents ML-based modeling approaches that efficiently characterize SI and PI behavior in systems with meshed planes.

ANN Architecture and Hyperparameter Optimization

Artificial neural network (ANN) models are developed for pre-layout SI analysis of traces referenced to meshed ground planes. These models offer sufficient flexibility to approximate the nonlinear relationships between meshed-plane geometry and EM response. However, model performance is strongly influenced by hyperparameter selection, including hidden layer count, hidden dimension, learning rate, and training epochs.

Rather than relying on manual tuning or grid search, Gaussian process-based Bayesian optimization is employed to identify optimal ANN hyperparameters.

ML Models for Pre-Layout SI Analysis

To address these challenges, ML models are being introduced as surrogate models for EM-based SI analysis. They focus on traces referenced to meshed ground planes, particularly cross-hatch structures commonly used in flexible and rigid-flex boards. The outputs of the model include per-unit-length inductance and capacitance, single-ended trace impedance, propagation delay, and velocity, differential and common-mode impedance for coupled traces, and differential delay and delay mismatch. These outputs directly support pre-layout SI analysis and constraint definition.

The methods proposed in the article demonstrate high accuracy compared with 3D full-wave EM simulations, while achieving orders-of-magnitude reduction in computation time. The advantages are:

Systematic exploration of the hyperparameter space
Flexible search domains, allowing continuous parameter ranges rather than discretized values
Efficient convergence, achieving improved accuracy with fewer training iterations

Notably, the hidden layer dimensions are not constrained to traditional powers-of-two conventions, enabling more efficient network configurations.

The results suggest that ML-enabled modeling can serve as a practical and scalable solution for SI/PI analysis of complex meshed-plane structures.

Conclusion

Meshed planes are becoming indispensable in modern electronic systems, yet they pose significant challenges for conventional SI and PI analysis methodologies. This article has discussed how ML-based modeling, combined with systematic hyperparameter optimization, offers a practical and accurate alternative to brute-force EM simulation. By enabling fast and reliable prediction of key SI metrics for traces referenced to meshed planes, the proposed approach supports efficient design-space exploration and informed engineering decision-making.

View the complete article and learn more about the Cadence Clarity 3D EM Solver, employed for the analysis of the models discussed in the article.

Mastering Library Development in Allegro X System Capture

Priyadarshini N D — Mon, 27 Apr 2026 20:30:00 GMT

Modern schematic-driven design flows rely on accurate, reusable, and well-structured libraries to ensure design correctness, consistency, and smooth downstream PCB implementation. In Cadence's Allegro X System Capture, library development forms the foundation of an efficient design process, enabling seamless schematic creation, constraint application, and PCB implementation.

Join us for this free Cadence technical training webinar with Priyadarshini N D, where we dive into the library development flow in Allegro X System Capture. By adopting best practices, designers can reduce errors, improve collaboration, accelerate schematic creation, and ensure a smooth transition from concept to layout and fabrication.

Agenda:

Creating accurate symbols: Correct pin definitions, electrical types, and visibility
Logical-to-physical mapping: Between schematic symbols and PCB packages
Authoring multiple package symbols: Including single and multiple packages
Creating split symbols: Symmetrical and asymmetrical
Spreadsheet‑based symbol creation for faster and more consistent library development

Date and Time:

Wednesday, May 20

07:00 – 08:00 PDT San Jose / 10:00 – 11:00 EDT New York / 15:00 – 16:00 BST London / 16:00 – 17:00 CEST Berlin / 17:00 – 18:00 IDT Jerusalem / 19:30 – 20:30 IST Bengaluru (Bangalore) / 22:00 – 23:00 CST Beijing

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