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<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/atom.xsl" media="screen"?><feed xmlns="http://www.w3.org/2005/Atom" xml:lang="en-US"><title type="html">PCB、IC封装：设计与仿真分析</title><subtitle type="html" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/atom</id><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn" /><link rel="self" type="application/atom+xml" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/atom" /><generator uri="http://telligent.com" version="13.0.4.37021">Telligent Community (Build: 13.0.4.37021)</generator><updated>2023-12-07T09:08:00Z</updated><entry><title>在云中运行 Clarity 3D Solver，对复杂系统进行电磁分析</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/clarity_2d00_3d_2d00_solver_2d00_cloud_2d00_fem_2d00_zh" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/clarity_2d00_3d_2d00_solver_2d00_cloud_2d00_fem_2d00_zh</id><published>2026-10-23T01:00:00Z</published><updated>2026-10-23T01:00:00Z</updated><content type="html">
核心结论：Cadence Clarity 3D Solver Cloud 通过与 Amazon Web Services（AWS）的安全连接，将 3D 有限元法（FEM）电磁仿真容量从 32 个 CPU 内核扩展至数千。在 PCB 测试用例中，仿真速度提升 6 倍至 20 倍，内存使用减少 50% 至 75%；在 IC 封装测试用例中，平均性能提高 10 倍。
一、为什么复杂系统的 3D 电磁仿真需要云？
超大规模计算、航空航天、工业物联网（IIoT）和汽车等领域对智能系统的需求不断增加，设计...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/clarity_2d00_3d_2d00_solver_2d00_cloud_2d00_fem_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364454&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="自适应网格细化" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_EA810290945E517F3C68C67E1653_" /><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="Clarity 3D Solver Cloud" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Clarity%2b3D%2bSolver%2bCloud" /><category term="电磁分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_3575C17806529067_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="Clarity 3D Solver" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Clarity%2b3D%2bSolver" /><category term="3D 全波电磁求解器" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/3D%2b_6851E26C3575C178426CE3896856_" /><category term="有限元法" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_096750964351D56C_" /></entry><entry><title>Fidelity Pointwise 嵌套网格单元修复技术解析：提升 CFD 仿真精度与网格装配效率</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/fidelity_2d00_pointwise_2d00_grid_2d00_cell_2d00_remediation_2d00_method_2d00_overset_2d00_meshes_2d00_zh" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/fidelity_2d00_pointwise_2d00_grid_2d00_cell_2d00_remediation_2d00_method_2d00_overset_2d00_meshes_2d00_zh</id><published>2026-10-22T01:00:00Z</published><updated>2026-10-22T01:00:00Z</updated><content type="html">在计算流体力学（CFD）仿真领域，嵌套网格因能够高效处理运动部件、复杂几何以及多区域耦合问题，已广泛应用于涡轮机械、航空航天、旋转设备和流体动力学分析等场景。然而，嵌套网格技术长期面临一个关键挑战：不同组件网格之间的单元尺寸差异会影响求解精度，甚至导致网格装配失败和孤立网格问题。
Cadence Fidelity&amp;nbsp;Pointwise 通过自动化网格单元修复技术，为结构化和非结构化嵌套网格提供了一种高效解决方案。该方法能够自动识别通信区域附近的网格质量问题，并优化单元尺寸过渡，从而提高网...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/fidelity_2d00_pointwise_2d00_grid_2d00_cell_2d00_remediation_2d00_method_2d00_overset_2d00_meshes_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364453&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="CFD仿真" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/CFD_FF4E1F77_" /><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="计算流体力学" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_A18B977B416D534F9B52665B_" /><category term="涡轮机械分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_A16D6E8F3A67B06806529067_" /><category term="嵌套网格" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_4C5D5759517F3C68_" /><category term="网格单元修复" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C6855534351EE4F0D59_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="网格优化" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C68184F1653_" /></entry><entry><title>柔性 PCB 与刚柔结合 PCB 设计指南：从材料选择到制造交付的完整实践</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/rigid_2d00_flex_2d00_pcb_2d00_design_2d00_design_2d00_guide_2d00_zh" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/rigid_2d00_flex_2d00_pcb_2d00_design_2d00_design_2d00_guide_2d00_zh</id><published>2026-10-21T01:00:00Z</published><updated>2026-10-21T01:00:00Z</updated><content type="html">随着可穿戴设备、医疗电子、汽车电子及航空航天产品不断向轻量化、高集成化方向发展， 柔性 PCB 和刚柔结合 PCB 正在成为越来越重要的设计方案。 与传统刚性电路板相比，这类设计能够显著减少连接器和线缆数量，提升空间利用率、可靠性与产品集成度， 但同时也对材料、叠层结构、器件布局、布线规则以及制造文档提出了更高要求。

柔性 PCB 采用聚酰亚胺等柔性材料，可实现弯曲、折叠和扭转，在保持电气连接稳定的同时满足复杂机械结构需求。 而刚柔结合 PCB 则将刚性区域与柔性区域集成在同一块电路板中，可替...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/rigid_2d00_flex_2d00_pcb_2d00_design_2d00_design_2d00_guide_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364448&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="PCB布局布线" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_035E405C035EBF7E_" /><category term="PCB设计规范" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_BE8BA18BC4890383_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="PCB可制造性设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_EF53365220902760BE8BA18B_" /><category term="刚柔结合设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_1A52D467D37E0854BE8BA18B_" /><category term="柔性PCB" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D4672760_PCB" /><category term="刚柔结合" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_1A52D467D37E0854_" /></entry><entry><title>PCIe 5.0/6.0 设计指南：PCI-SIG 一致性测试、眼图分析与高速 PCB 设计实践</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/engineers_2d00_guide_2d00_to_2d00_pcie_2d00_zh_2d00_cn" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/engineers_2d00_guide_2d00_to_2d00_pcie_2d00_zh_2d00_cn</id><published>2026-10-20T01:00:00Z</published><updated>2026-10-20T01:00:00Z</updated><content type="html">随着 PCIe 5.0 和 PCIe 6.0 的普及，数据传输速率已从 PCIe 4.0 的 16GT/s 提升至 PCIe 6.0 的 64GT/s。 带宽不断提高的同时，信号完整性、时序控制和链路可靠性面临更严苛的挑战。 对于 AI 服务器、高性能计算（HPC）、GPU 加速卡、高速存储和网络设备而言，PCIe 链路质量直接影响产品性能、稳定性以及 PCI-SIG 一致性认证结果。

PCIe 一致性测试为什么重要？
PCIe 产品在发布前通常需要通过 PCI-SIG 规定的合规测试。 如果...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/engineers_2d00_guide_2d00_to_2d00_pcie_2d00_zh_2d00_cn"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364446&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="PCI-SIG规范" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCI_2D00_SIG_C4890383_" /><category term="PCIe认证" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCIe_A48BC18B_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="高速PCB设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90_PCB_BE8BA18B_" /><category term="PCIe 5.0设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCIe%2b5-0_BE8BA18B_" /></entry><entry><title>高速数字设计信号完整性分析解析</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/hsd_2d00_pcb_2d00_si_2d00_zh" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/hsd_2d00_pcb_2d00_si_2d00_zh</id><published>2026-10-19T01:00:00Z</published><updated>2026-10-19T01:00:00Z</updated><content type="html">在 PCIe Gen5/Gen6、DDR5、USB4、100G/400G 以太网、AI 服务器、高性能计算（HPC）以及数据中心设备设计中，PCB 已不仅仅是连接器件的载体，而是高速信号传输链路的重要组成部分。随着数据速率不断提升，信号完整性已经成为决定系统性能、稳定性和产品一次成功率的关键因素。
《HSD PCB 信号完整性分析指南》系统介绍了高速数字设计（High-Speed Digital，HSD）中最常见的信号完整性问题及其解决思路，包括阻抗控制、串扰分析、时序偏斜、返回路径以及同步开关...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/hsd_2d00_pcb_2d00_si_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364375&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="差分信号" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_EE5D0652E14FF753_" /><category term="时钟抖动分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_F6659F949662A85206529067_" /><category term="DDR5设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/DDR5_BE8BA18B_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="高速PCB设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90_PCB_BE8BA18B_" /><category term="同步开关噪声" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_0C54656B005F73516A56F058_" /><category term="PCB信号完整性分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_E14FF7538C5B7465276006529067_" /></entry><entry><title>先进封装热翘曲仿真：温度依赖材料模型如何提高预测精度？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1364359" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1364359</id><published>2026-09-09T03:30:00Z</published><updated>2026-09-09T03:30:00Z</updated><content type="html">随着芯粒、2.5D 封装、3D IC、AI 服务器以及高性能计算（HPC） 等先进封装技术快速发展，热翘曲已经成为影响产品可靠性、 组装良率和长期性能的重要因素。
在封装设计过程中，工程师通常会重点关注结温、 散热能力以及功耗问题，但实际上，材料之间的热膨胀系数（CTE）差异同样会导致严重的机械变形。 如果热翘曲预测不准确，可能引发焊点开裂、焊接失效以及封装可靠性下降等问题。

为什么先进封装会发生热翘曲？
先进封装结构往往包含裸片、基板、底部填充、 封装材料以及 PCB 等多种材料。
由于不同...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1364359"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364359&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="热翘曲仿真" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_ED70D87FF266FF4E1F77_" /><category term="温度依赖材料模型" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_296EA65E9D4F568D50679965216A8B57_" /><category term="2.5D封装热分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/2-5D_015CC588ED7006529067_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="热膨胀系数" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_ED70A881C080FB7C7065_" /><category term="先进封装热分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_4851DB8F015CC588ED7006529067_" /><category term="封装可靠性分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_015CC588EF536097276006529067_" /></entry><entry><title>PCB 设计数据越来越复杂，工程团队为什么还在用传统文件管理方式？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/pcb-1856799362" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/pcb-1856799362</id><published>2026-09-08T03:30:00Z</published><updated>2026-09-08T03:30:00Z</updated><content type="html">随着 PCB 设计规模持续扩大，企业正在产生前所未有数量的设计数据。从原理图、PCB数据库、元件库、BOM，到制造文件、仿真模型、机械协同数据，工程团队每天都在与海量设计信息打交道。
然而，一个经常被忽视的问题是：当设计越来越复杂，传统的数据管理方式是否还能支撑现代电子产品开发？


图1：Allegro X Pulse 智能仪表板界面
为什么 PCB 设计数据管理正在成为新的工程挑战？
在许多企业中，设计数据仍然依赖工程师自行整理、共享和维护。随着项目成员增多、设计版本增加以及跨部门协作频繁，...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/pcb-1856799362"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364349&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="工程协同" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_E55D0B7A4F530C54_" /><category term="PCB设计流程优化" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_BE8BA18B416D0B7A184F1653_" /><category term="PCB Data Management" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB%2bData%2bManagement" /><category term="设计数据自动化" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_BE8BA18B70656E63EA81A8521653_" /><category term="PCB设计数据管理" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_BE8BA18B70656E63A17B0674_" /></entry><entry><title>为什么只做 SI 或 PI 仿真，已经不足以支撑高速设计签核？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/sigrity_2d00_power_2d00_aware_2d00_analysis_2d00_solution_2d00_zh" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/sigrity_2d00_power_2d00_aware_2d00_analysis_2d00_solution_2d00_zh</id><published>2026-09-07T04:30:00Z</published><updated>2026-09-07T04:30:00Z</updated><content type="html">随着 SerDes、DDR5、224Gbps 高速链路等技术快速发展，PCB 设计中的信号完整性（SI）与电源完整性（PI）之间的关系越来越紧密。然而，许多工程师的分析流程仍停留在&amp;ldquo;SI 归 SI、PI 归 PI&amp;rdquo;的阶段，导致一些关键问题难以在签核前被发现。Cadence 白皮书指出，未来的高速设计验证，必须从传统的 SI 分析升级到&amp;ldquo;兼顾电源影响&amp;rdquo;分析。
高速设计正在进入&amp;ldquo;电源影响时代&amp;rdquo;
过去三十年，高速数字系统的数据速率...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/sigrity_2d00_power_2d00_aware_2d00_analysis_2d00_solution_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364303&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="ddr5" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/ddr5" /><category term="PDN" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PDN" /><category term="Sigrity X" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Sigrity%2bX" /><category term="高速设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90BE8BA18B_" /><category term="DRC" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/DRC" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="兼顾电源影响的SI" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7C517E983575906E715FCD548476_SI" /><category term="SSN分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/SSN_06529067_" /><category term="SI分析与建模" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/SI_065290670E4EFA5E216A_" /></entry><entry><title>3D-IC 热设计新挑战：RISC-V 多核 SoC 如何通过功能分区优化散热？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/thermal_2d00_analysis_2d00_3d_2d00_and_2d00_beol_2d00_zh" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/thermal_2d00_analysis_2d00_3d_2d00_and_2d00_beol_2d00_zh</id><published>2026-08-19T07:40:00Z</published><updated>2026-08-19T07:40:00Z</updated><content type="html">随着 AI 推理、高性能计算（HPC）以及 RISC-V 多核架构快速发展，芯片计算能力不断提升，但热管理问题却逐渐成为影响性能释放的关键瓶颈。
传统 2D SoC 虽然持续受益于先进工艺节点，但布线拥塞、功耗密度增加以及散热能力受限等问题愈发明显。为了突破这些限制，3D-IC、混合键合（Hybrid Bonding）和背面供电网络（BSPDN）等先进封装技术正成为半导体行业重点关注方向。
为什么 3D-IC 会带来新的热设计挑战？
3D 堆叠技术通过将多个裸片垂直集成，显著缩短信号传输距离，提...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/thermal_2d00_analysis_2d00_3d_2d00_and_2d00_beol_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364312&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="热分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_ED7006529067_" /><category term="3D-IC" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/3D_2D00_IC" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /></entry><entry><title>存储接口设计为何不能再忽略电源噪声？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_aware_2d00_challenges_2d00_memory_2d00_interface_2d00_designs_2d00_zh" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_aware_2d00_challenges_2d00_memory_2d00_interface_2d00_designs_2d00_zh</id><published>2026-08-18T08:46:00Z</published><updated>2026-08-18T08:46:00Z</updated><content type="html">从&amp;ldquo;信号完整性&amp;rdquo;走向&amp;ldquo;兼顾电源影响的信号完整性分析&amp;rdquo;
随着 DDR4、LPDDR4 等高速存储接口速率持续提升，工程师面临的挑战已不仅是阻抗控制和布线优化，更重要的是在分析信号的同时，将电源分配网络（PDN）对系统性能的影响纳入考虑。
传统信号完整性（SI）分析往往假设电源和地网络是理想的，但在实际系统中，大量数据线同步切换会产生同步开关噪声（SSN），导致电源轨和地轨出现电压波动，进而影响时序裕量和数据可靠性。

图1：理想与非理想 PDN 假设...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_aware_2d00_challenges_2d00_memory_2d00_interface_2d00_designs_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364304&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="DDR4" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/DDR4" /><category term="存储接口设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_585BA850A563E353BE8BA18B_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="信号完整性" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_E14FF7538C5B74652760_" /></entry><entry><title>电动汽车电源模块设计：如何同时解决可靠性与安全性问题？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_module_2d00_design_2d00_for_2d00_ev_2d00_zh" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_module_2d00_design_2d00_for_2d00_ev_2d00_zh</id><published>2026-08-14T08:30:00Z</published><updated>2026-08-14T08:30:00Z</updated><content type="html">随着电动汽车续航里程和快充需求不断提升，功率器件正向更高电压、更高电流和更高功率密度演进。但与此同时，电源模块的可靠性挑战也愈发严峻。一个看似微小的封装缺陷或散热问题，都可能导致系统失效，甚至影响整车安全。
现代电动汽车广泛采用 SiC（碳化硅）MOSFET，以降低开关损耗和导通损耗，从而提升能源利用效率和续航能力。然而，高功率密度也意味着：

工作温度可接近甚至超过 130&amp;deg;C
电压可达 600V 以上
电流可达数十安培
电磁干扰（EMI）问题更加突出
结构应力和长期可靠性风险增加

...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_module_2d00_design_2d00_for_2d00_ev_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364302&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="热分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_ED7006529067_" /><category term="汽车电子" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7D6C668F3575505B_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /></entry><entry><title>AI/ML 如何优化 IBIS-AMI 模型参数？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/optimization_2d00_of_2d00_ibis_2d00_ami_2d00_model_2d00_parameters_2d00_with_2d00_ml" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/optimization_2d00_of_2d00_ibis_2d00_ami_2d00_model_2d00_parameters_2d00_with_2d00_ml</id><published>2026-08-13T11:42:00Z</published><updated>2026-08-13T11:42:00Z</updated><content type="html">摘要
随着高速串行链路速率持续提升，IBIS-AMI 模型的参数空间变得更加复杂。传统手动寻优需要大量仿真，成本高且效率低。本文结合 Cadence Sigrity X SI/PI 机器学习优化算法，说明如何在更少仿真次数下寻找 AMI 参数的理想组合，并帮助接收端获得更好的眼图开口。
为什么 IBIS-AMI 参数优化越来越难？
在高速串行链路设计中，链路速率、通道损耗、均衡策略和模型参数范围都会直接影响信号完整性分析结果。过去不到20年，串行链路速度已经大幅提升，IBIS-AMI模型也随之变...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/optimization_2d00_of_2d00_ibis_2d00_ami_2d00_model_2d00_parameters_2d00_with_2d00_ml"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364293&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="ml" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/ml" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="Sigrity" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Sigrity" /><category term="信号完整性" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_E14FF7538C5B74652760_" /></entry><entry><title>如何在高速信号中降低符号间干扰</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360780" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360780</id><published>2023-12-19T14:06:00Z</published><updated>2023-12-19T14:06:00Z</updated><content type="html">在考虑高速通道中影响 PCB 信号完整性的问题时，特别应该诊断的是符号间干扰。这种特定的信号完整性问题涉及比特流中信号之间的干扰。那么，符号间干扰是什么？其产生的原因是什么？有什么方法减少信号干扰，保持高速设计中的信号完整性？本文将讨论如何在高速通道中减少符号间干扰。(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360780"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360780&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Sigrity</name><uri>https://community.cadence.com/members/sigrity</uri></author><category term="PCB" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB" /><category term="串扰" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_324E7062_" /><category term="SI" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/SI" /><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="仿真分析" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_FF4E1F7706529067_" /><category term="符号间干扰" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_267BF753F495725E7062_" /><category term="高速互连设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90924EDE8FBE8BA18B_" /><category term="高速信号" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90E14FF753_" /><category term="高速设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90BE8BA18B_" /><category term="PCB设计" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_BE8BA18B_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="Sigrity" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Sigrity" /><category term="crosstalk" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/crosstalk" /><category term="信号完整性" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_E14FF7538C5B74652760_" /></entry><entry><title>如何在 CFD 设计中利用网格维护几何形状并减少运行时间？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/cfd-1189615426" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/cfd-1189615426</id><published>2023-12-18T13:28:00Z</published><updated>2023-12-18T13:28:00Z</updated><content type="html">在 CFD 仿真中，求解的质量在很大程度上取决于网格划分。网格间距如果不能求解流体变量的局部变化，就会引入离散化误差。但如果网格过于精细，就会增加不必要的计算时间和工作量。网格元素类型和数据结构也会影响生成网格所需的人力时间和技能，以及单位精度的成本。本文介绍了网格自适应技术的挑战与 Fidelity Pointwise 解决方案。(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/cfd-1189615426"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360779&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="网格划分" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C6812520652_" /><category term="CFD" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/CFD" /><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="计算流体力学" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_A18B977B416D534F9B52665B_" /><category term="网格生成" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C681F751062_" /><category term="网格自适应" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C68EA810290945E_" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="Fidelity CFD" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Fidelity%2bCFD" /><category term="汽车" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7D6C668F_" /><category term="Fidelity Pointwise" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Fidelity%2bPointwise" /></entry><entry><title>什么是网格划分或网格生成？</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360778" /><id>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360778</id><published>2023-12-07T09:08:00Z</published><updated>2023-12-07T09:08:00Z</updated><content type="html">庞杂的几何文件、复杂的几何结构，使得 CFD 仿真在网格制作上极其耗时。如何解放工程师的双手， 把更多的精力投入到结果分析和创新性能设计上？本文简述了网格划分的基本概念、进行网格划分的重要性和生成高保真网络的基本流程。(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360778"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360778&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>SDA China</name><uri>https://community.cadence.com/members/sda-china</uri></author><category term="网格划分" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C6812520652_" /><category term="CFD" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/CFD" /><category term="Chinese blog" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog" /><category term="计算流体力学" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_A18B977B416D534F9B52665B_" /><category term="CFD应用" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/CFD_945E2875_" /><category term="Fidelity Automesh" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Fidelity%2bAutomesh" /><category term="中文" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_" /><category term="汽车" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7D6C668F_" /><category term="流体求解器" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_416D534F426CE3896856_" /><category term="Fidelity Pointwise" scheme="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Fidelity%2bPointwise" /></entry></feed>