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<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>PCB、IC封装：设计与仿真分析</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 19 Aug 2026 07:40:00 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://community.cadence.com/cadence_blogs_8/b/pcbchn" /><item><title>3D-IC 热设计新挑战：RISC-V 多核 SoC 如何通过功能分区优化散热？</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/thermal_2d00_analysis_2d00_3d_2d00_and_2d00_beol_2d00_zh</link><pubDate>Wed, 19 Aug 2026 07:40:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d545ac97-489b-42ab-9396-ff6ec1cb0931</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>随着 AI 推理、高性能计算（HPC）以及 RISC-V 多核架构快速发展，芯片计算能力不断提升，但热管理问题却逐渐成为影响性能释放的关键瓶颈。
传统 2D SoC 虽然持续受益于先进工艺节点，但布线拥塞、功耗密度增加以及散热能力受限等问题愈发明显。为了突破这些限制，3D-IC、混合键合（Hybrid Bonding）和背面供电网络（BSPDN）等先进封装技术正成为半导体行业重点关注方向。
为什么 3D-IC 会带来新的热设计挑战？
3D 堆叠技术通过将多个裸片垂直集成，显著缩短信号传输距离，提...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/thermal_2d00_analysis_2d00_3d_2d00_and_2d00_beol_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364312&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_ED7006529067_">热分析</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/3D_2D00_IC">3D-IC</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category></item><item><title>存储接口设计为何不能再忽略电源噪声？</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_aware_2d00_challenges_2d00_memory_2d00_interface_2d00_designs_2d00_zh</link><pubDate>Tue, 18 Aug 2026 08:46:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6ccac5ae-7d1d-4116-8e1a-23e34e07c5dd</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>从&amp;ldquo;信号完整性&amp;rdquo;走向&amp;ldquo;兼顾电源影响的信号完整性分析&amp;rdquo;
随着 DDR4、LPDDR4 等高速存储接口速率持续提升，工程师面临的挑战已不仅是阻抗控制和布线优化，更重要的是在分析信号的同时，将电源分配网络（PDN）对系统性能的影响纳入考虑。
传统信号完整性（SI）分析往往假设电源和地网络是理想的，但在实际系统中，大量数据线同步切换会产生同步开关噪声（SSN），导致电源轨和地轨出现电压波动，进而影响时序裕量和数据可靠性。

图1：理想与非理想 PDN 假设...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_aware_2d00_challenges_2d00_memory_2d00_interface_2d00_designs_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364304&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/DDR4">DDR4</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_585BA850A563E353BE8BA18B_">存储接口设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_E14FF7538C5B74652760_">信号完整性</category></item><item><title>为什么只做 SI 或 PI 仿真，已经不足以支撑高速设计签核？</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/sigrity_2d00_power_2d00_aware_2d00_analysis_2d00_solution_2d00_zh</link><pubDate>Mon, 17 Aug 2026 08:30:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:66106ff1-931d-49eb-b423-4d352a413151</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>随着 SerDes、DDR5、224Gbps 高速链路等技术快速发展，PCB 设计中的信号完整性（SI）与电源完整性（PI）之间的关系越来越紧密。然而，许多工程师的分析流程仍停留在&amp;ldquo;SI 归 SI、PI 归 PI&amp;rdquo;的阶段，导致一些关键问题难以在签核前被发现。Cadence 白皮书指出，未来的高速设计验证，必须从传统的 SI 分析升级到&amp;ldquo;兼顾电源影响&amp;rdquo;分析。
高速设计正在进入&amp;ldquo;电源影响时代&amp;rdquo;
过去三十年，高速数字系统的数据速率...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/sigrity_2d00_power_2d00_aware_2d00_analysis_2d00_solution_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364303&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90BE8BA18B_">高速设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/SI_065290670E4EFA5E216A_">SI分析与建模</category></item><item><title>电动汽车电源模块设计：如何同时解决可靠性与安全性问题？</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_module_2d00_design_2d00_for_2d00_ev_2d00_zh</link><pubDate>Fri, 14 Aug 2026 08:30:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e3990a50-4d0f-47d7-8abd-308330e32ac7</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>随着电动汽车续航里程和快充需求不断提升，功率器件正向更高电压、更高电流和更高功率密度演进。但与此同时，电源模块的可靠性挑战也愈发严峻。一个看似微小的封装缺陷或散热问题，都可能导致系统失效，甚至影响整车安全。
现代电动汽车广泛采用 SiC（碳化硅）MOSFET，以降低开关损耗和导通损耗，从而提升能源利用效率和续航能力。然而，高功率密度也意味着：

工作温度可接近甚至超过 130&amp;deg;C
电压可达 600V 以上
电流可达数十安培
电磁干扰（EMI）问题更加突出
结构应力和长期可靠性风险增加

...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/power_2d00_module_2d00_design_2d00_for_2d00_ev_2d00_zh"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364302&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_ED7006529067_">热分析</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7D6C668F3575505B_">汽车电子</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category></item><item><title>AI/ML 如何优化 IBIS-AMI 模型参数？</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/optimization_2d00_of_2d00_ibis_2d00_ami_2d00_model_2d00_parameters_2d00_with_2d00_ml</link><pubDate>Thu, 13 Aug 2026 11:42:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:332f34f8-7cd0-4def-8599-f544128b74f4</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>摘要
随着高速串行链路速率持续提升，IBIS-AMI 模型的参数空间变得更加复杂。传统手动寻优需要大量仿真，成本高且效率低。本文结合 Cadence Sigrity X SI/PI 机器学习优化算法，说明如何在更少仿真次数下寻找 AMI 参数的理想组合，并帮助接收端获得更好的眼图开口。
为什么 IBIS-AMI 参数优化越来越难？
在高速串行链路设计中，链路速率、通道损耗、均衡策略和模型参数范围都会直接影响信号完整性分析结果。过去不到20年，串行链路速度已经大幅提升，IBIS-AMI模型也随之变...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/optimization_2d00_of_2d00_ibis_2d00_ami_2d00_model_2d00_parameters_2d00_with_2d00_ml"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364293&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/ml">ml</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Sigrity">Sigrity</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_E14FF7538C5B74652760_">信号完整性</category></item><item><title>如何在高速信号中降低符号间干扰</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360780</link><pubDate>Tue, 19 Dec 2023 14:06:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:38a04543-bde2-4224-a52b-4381fc24f207</guid><dc:creator>Sigrity</dc:creator><slash:comments>0</slash:comments><description>在考虑高速通道中影响 PCB 信号完整性的问题时，特别应该诊断的是符号间干扰。这种特定的信号完整性问题涉及比特流中信号之间的干扰。那么，符号间干扰是什么？其产生的原因是什么？有什么方法减少信号干扰，保持高速设计中的信号完整性？本文将讨论如何在高速通道中减少符号间干扰。(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360780"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360780&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB">PCB</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_324E7062_">串扰</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/SI">SI</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_FF4E1F7706529067_">仿真分析</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_267BF753F495725E7062_">符号间干扰</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90924EDE8FBE8BA18B_">高速互连设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90E14FF753_">高速信号</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_D89A1F90BE8BA18B_">高速设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_BE8BA18B_">PCB设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Sigrity">Sigrity</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/crosstalk">crosstalk</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_E14FF7538C5B74652760_">信号完整性</category></item><item><title>如何在 CFD 设计中利用网格维护几何形状并减少运行时间？</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/cfd-1189615426</link><pubDate>Mon, 18 Dec 2023 13:28:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6f174689-ae00-491c-81a0-188136056294</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>在 CFD 仿真中，求解的质量在很大程度上取决于网格划分。网格间距如果不能求解流体变量的局部变化，就会引入离散化误差。但如果网格过于精细，就会增加不必要的计算时间和工作量。网格元素类型和数据结构也会影响生成网格所需的人力时间和技能，以及单位精度的成本。本文介绍了网格自适应技术的挑战与 Fidelity Pointwise 解决方案。(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/cfd-1189615426"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360779&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C6812520652_">网格划分</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/CFD">CFD</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_A18B977B416D534F9B52665B_">计算流体力学</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C681F751062_">网格生成</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C68EA810290945E_">网格自适应</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Fidelity%2bCFD">Fidelity CFD</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7D6C668F_">汽车</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Fidelity%2bPointwise">Fidelity Pointwise</category></item><item><title>什么是网格划分或网格生成？</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360778</link><pubDate>Thu, 07 Dec 2023 09:08:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f9bbebcd-9227-42d6-8eea-49b9dd3c60a9</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>庞杂的几何文件、复杂的几何结构，使得 CFD 仿真在网格制作上极其耗时。如何解放工程师的双手， 把更多的精力投入到结果分析和创新性能设计上？本文简述了网格划分的基本概念、进行网格划分的重要性和生成高保真网络的基本流程。(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360778"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360778&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_517F3C6812520652_">网格划分</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/CFD">CFD</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_A18B977B416D534F9B52665B_">计算流体力学</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/CFD_945E2875_">CFD应用</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Fidelity%2bAutomesh">Fidelity Automesh</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7D6C668F_">汽车</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_416D534F426CE3896856_">流体求解器</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Fidelity%2bPointwise">Fidelity Pointwise</category></item><item><title>释放 AI 大模型潜能，硬件算力亟待突破互连瓶颈</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/ai</link><pubDate>Sat, 02 Dec 2023 03:30:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:28002e6c-8507-4bff-b6f0-42e086a5d575</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>完全可以预期，在 OpenAI 明星效应下，全球科技巨头未来一两年必将推出一系列类 GPT 预训练大模型，也有望带动对数据中心 AI 算力集群的投资进一步加速。随着 AI 大模型揭示的全新想象空间出现，算力集群这一基础设施也将迎来投资热潮，而在其面临的配电、散热、通信等一系列工程挑战中，算力节点间的数据传输尤其堪称制约硬件算力充分释放的关键“瓶颈”。(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/ai"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360724&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/SI">SI</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Allegro%2bX%2bAI">Allegro X AI</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_BE8BA18B_">PCB设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/112g">112g</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/SerDes">SerDes</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Allegro%2bX%2b23-1">Allegro X 23.1</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_E14FF7538C5B74652760_">信号完整性</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/AI">AI</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/allegro%2bx">allegro x</category></item><item><title>详解高密 PCB 走线布线的垂直导电结构 (VeCS)</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/pcb-vecs</link><pubDate>Fri, 01 Dec 2023 07:19:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5f7e369c-1b84-47d5-8966-8d9a2e29a428</guid><dc:creator>TeamAllegro</dc:creator><slash:comments>0</slash:comments><description>本文要点：&amp;bull; 什么是垂直导电结构 (Vertical Conductive Structures, VeCS)及其工作原理。&amp;bull; 利用 VeCS 进行 PCB 设计的优势。&amp;bull; 使用 VeCS 技术设计电路板的后续步骤。
长久以来，我们不断努力改进电路板的设计和构建&amp;mdash;&amp;mdash;从通孔到表面贴装元件，从双层电路板到多层电路板，从普通导线走线到高密布线。想想如今，似乎已没有什么可供一试的新鲜技术，但其实并不然。
一块高速高密印刷电路板。
为了尽可能有效地利用...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/pcb-vecs"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360547&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_BE8BA18B_">PCB设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Layout">Layout</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Allegro%2bX%2b23-1">Allegro X 23.1</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_035E405C035EBF7E_">布局布线</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_8257F476FC5B3575D37E8467_">垂直导电结构</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/allegro%2bx">allegro x</category></item><item><title>Allegro X——新一代智能系统设计平台</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/allegro-x</link><pubDate>Thu, 09 Nov 2023 08:43:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cd49acab-f6d4-4140-8cad-c9883c7911c2</guid><dc:creator>TeamAllegro</dc:creator><slash:comments>0</slash:comments><description>本文翻译自Cadence &amp;ldquo;Breakfast Bytes Blogs&amp;rdquo;专栏作者Paul McLellan文章&amp;ldquo; &lt;a href="https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/allegro-x" rel="noopener noreferrer" target="_blank"&gt;Allegro X, the Design Platform for the Next Generation of Intelligent System Design&lt;/a&gt;&amp;quot;。
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Cadence在打造大多数软件时都有一个共同的思路：将软件原生地集成在通用数据库上，以避免数据库转换可能造成的信息误差。这就好比当我们想用翻译软件把文字从法...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/allegro-x"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1353868&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB">PCB</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Allegro%2b23-1">Allegro 23.1</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_9F530674FE56BE8BA18B_">原理图设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_3A676856665B604E_">机器学习</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_035EBF7E_">布线</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_FB7CDF7EBE8BA18B_">系统设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_70656E63A17B0674_">数据管理</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB%2b_3A676856665B604E_">PCB 机器学习</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PCB_BE8BA18B_">PCB设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Layout">Layout</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Allegro%2bX%2b23-1">Allegro X 23.1</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7A66FD80BE8BA18B_">智能设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/allegro%2bx">allegro x</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_F76D0854914E_">混合云</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/X%2bAI">X AI</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Allegro">Allegro</category></item><item><title>用于蜂窝式物联网应用的多波段有源天线调谐器</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360665</link><pubDate>Fri, 13 Oct 2023 13:12:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8aedd69c-cdcb-4878-8d39-ffd1df61067a</guid><dc:creator>SDA China</dc:creator><slash:comments>0</slash:comments><description>伴随每一代无线电技术的问世，都涌现出了新的服务和业务机会，引领了所谓的“第三次通信浪潮”。由 5G 和未来 6G 技术赋能的技术革新将为更多行业和社会新型服务提供支持，直到 2030 年及以后。本文讨论了为蜂窝式物联网 (IoT) 大规模机器类通信 (mMTC) 应用开发多频段有源天线调谐器的相关设计挑战和解决方案。(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360665"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360665&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_045C9198_">射频</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/5G">5G</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_AE5FE26C_">微波</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_FB79A8521A90E14F_">移动通信</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/awr">awr</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/IoT">IoT</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_69725480517F_">物联网</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2959BF7E_">天线</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/AWR%2bMicrowave%2bOffice">AWR Microwave Office</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_735E62973575C17806529067_">平面电磁分析</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_1A90E14F_">通信</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7A66FD80FB7CDF7EBE8BA18B_">智能系统设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Clarity%2b3D%2bSolver">Clarity 3D Solver</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_02879D7A0F5F69725480517F_">蜂窝式物联网</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/AWR%2bAXIEM%2b3D">AWR AXIEM 3D</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/6G">6G</category></item><item><title>汽车 EMC 问题一览</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/emc</link><pubDate>Fri, 13 Oct 2023 09:30:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:35b8a889-676b-4f2c-921a-265f2ec601fe</guid><dc:creator>Sigrity</dc:creator><slash:comments>0</slash:comments><description>汽车 EMC 问题是仅次于尾气排放和交通噪音的第三大车辆污染形式。与传统的内燃机汽车相比，电动或混合动力汽车更容易受到汽车 EMC 问题的困扰。本文将探讨汽车常见 EMC 问题以及 EMC 的来源。 (&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/emc"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360664&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/EMI">EMI</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Clarity%2b3D%2bTransient%2bSolver">Clarity 3D Transient Solver</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/FDTD">FDTD</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/FEM">FEM</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/EMC">EMC</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_3575C178FF4E1F77_">电磁仿真</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_FB7CDF7E06529067_">系统分析</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7D6C668F_">汽车</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_7A66FD80FB7CDF7EBE8BA18B_">智能系统设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Clarity%2b3D%2bSolver">Clarity 3D Solver</category></item><item><title>如何在封装设计中创建并使用非圆形过孔堆叠？</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360603</link><pubDate>Mon, 11 Sep 2023 06:14:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:860c349a-5dc6-41ad-8b3e-40c587dc0f14</guid><dc:creator>TeamAllegro</dc:creator><slash:comments>0</slash:comments><description>要设计出尺寸更小的电子器件，可以在多层基板或多层印刷电路板 (PCB) 中采用高密度设计，增加每层的使用率。在多层封装或多层电路板的设计和制造过程中，过孔的作用不可或缺。我们需要使用过孔或电镀过孔来实现从一层到另一层的布线。虽然也可以使用通孔或盲孔，但这两种孔占用了过多的空间，使得复杂和高密度电子器件难以布线。要解决这个问题，可以使用堆叠的过孔，即两个或两个以上的分层过孔彼此堆叠在一起。
在本文中，我们将借助 Allegro Package Designer Plus 工具，探讨如何在高密度复杂...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360603"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360603&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/IC_015CC588BE8BA18B_">IC封装设计</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_6F8FF64E8062E75D_">软件技巧</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Allegro%2bPackage%2bDesigner%2bPlus">Allegro Package Designer Plus</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Allegro">Allegro</category></item><item><title>信号如何在无限大的导电介质中传播</title><link>https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360570</link><pubDate>Fri, 25 Aug 2023 09:31:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f17337a6-907b-4761-b078-613e5fcff935</guid><dc:creator>Sigrity</dc:creator><slash:comments>0</slash:comments><description>本文要点：

PCB 上的传输线是波导的一种形式，沿着波导的边界形成了一个开放的谐振器结构。
铜所具有的非理想性质会改变传输线结构中的典型波导行为。
一般传输线的阻抗可以通过考虑波的传播行为来计算，前提是必须兼顾导体的非理想性质。

传输线有许多种形式，如同轴线、印刷电路板上的印刷走线，或是长电缆或电线。这些结构都有一些类似的行为，涉及到电磁波如何沿互连线传播。尽管这些结构是引导电磁扰动沿互连线传播的基础，但对于信号如何在传输线上传播，人们往往存在误解。
具体而言，互连线上的电磁信号存在于线路的...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/1360570"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1360570&amp;AppID=114&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/SI">SI</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/PI">PI</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Chinese%2bblog">Chinese blog</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/Sigrity%2bX">Sigrity X</category><category domain="https://community.cadence.com/cadence_blogs_8/b/pcbchn/archive/tags/_2D4E8765_">中文</category></item></channel></rss>