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This is the third in a series of
discussions we would like to open up regarding "favorite features" in an IC
Packaging implementation design tool.
As the industry continues to
include larger numbers of larger die in a smaller IC package, the question of
"Can this be manufactured?" rings ever louder. No one likes to have their
artwork reviewed by the manufacturer and receive the news that things have to
change. It only has to happen once before the Assembly Rule Checks in
Cadence IC Packaging tools becomes a favorite feature.
The objective of the Assembly Rule
Checks is to go beyond what the design environment could provide in an online
DRC environment. As many of these checks look at the three-dimensional
die stack, it was not practical to have this kind of checking occurring in real
Thanks to collaboration with some
of the largest semiconductor companies in the world, the Cadence IC Packaging
design tools have a rich set of batch oriented assembly rule checks that help
tighten the loop between design and manufacturing.
As no package designer wants to be
the cause of a delay in getting a design to volume manufacturing, we choose
Assembly Rule Checks as a favorite feature in an IC Package design solution.
Please take six and one-half
minutes of your time to watch the video below, and you will see why IC Package
designers love the convenience of performing Assembly Rule Checks from the
If the video fails to play click here.
Let us know what Assembly Rule
Checks help you get your products to volume manufacturing faster.