Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Designing an IC package substrate is a complex task. From picking the right materials and substrate cross-section to configuring your design rule constraints and identifying your voltage nets, it can be easy to make a mistake no matter how careful you are. We are humans, after all.
Not all of these changes are obvious errors, either. Picking the wrong JEDEC package may be obvious after you place your die and see their relative sizes. Failing to identify a power or ground net can be far less noticeable until you try to route the net and the system seems sluggish or shows the wrong padstacks available for your vias.
Enter the Package Design Integrity Checker tool. Available in all Cadence APD and SiP package layout tools, this command scans your active drawing looking for common problems that may exist. These checks encompass a broad range of frequent setup errors: from unidentified voltage nets which will impact your routing and SI extraction performance, to bond wires that are not connected to a finger or pin on both ends, and even to missing dielectrics in your cross-section. These checks complement and extend the database doctor command, which searches strictly for database problems and not configuration problems.
Read on to learn more about how this command can help you catch errors earlier, fix them faster, and even prevent you from encountering them in the future.
The Package Design Integrity Checks, as we mentioned early, are there to help you find and fix problems that may not be obvious to you from looking at your design, but which can cause commands to behave strangely - sometimes even inaccurately - because the design data doesn't match your intentions.
When you open the command, the interface below is shown. The checks are broken into various categories so that, if you're having a problem with a specific area of the tool (e.g. your SI extraction is taking forever or giving you obviously incorrect outputs), you can choose to run just the checks for that category. Or, if you want to run a general health check-up on your design, run all the rules. Whatever you pick, you have the choice of having the tool write the results to a log file or create DRC markers into the design for you to see and correct.
For many rules, the tool can even correct the problems automatically for you. If a via is slightly offset from the origin of the BGA ball it connects to, the tool can shift it to the right location, stretching any cline connections to maintain connectivity. It is, however, always advisable that you run the checks in check-only mode first to verify that the changes it finds are not something you did intentionally.
Whatever checks you opt to run, you can get a detailed description directly in the UI (and in the log file, alongside all the rule violations found) describing the problem, what kind of problems it can lead to in the course of your package design flow, and the most common ways the problem can be created. In this way, not only can you fix your design in the minimum amount of time, you will know what you need to do earlier in your flow to prevent the problem in future designs.
If you have an idea for an Integrity Check rule that is a common error at your company and for the design community in general, let your customer support representative know. Or, consider posting about it in the public IC Packaging forums and see what your peers think.
But, if you have your own internal checks and rules that are proprietary knowledge for your company, you can still integrate those checks directly into the Package Integrity UI and infrastructure! Cadence provides a public Skill API to add your own custom categories and rules to the Checker so your specific conditions can be verified in the very same way as the core Cadence-provided functionality.
Have a comment? We'd love to hear from you!