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If you are using Allegro® Package Designer Plus with the Silicon Layout option to design your substrates, it is likely that you are also using a formal verification platform such as Cadence Pegasus or PVS to check your physical layout against the logical schematic.
To do this, you will need to export a set of data files from your layout database:
A GDSII file describing all the physical geometries,
A CDL netlist describing the physical connectivity and any pseudo resistors,
(Optionally) A PVS Stacked Die Report describing relative component placements, orientations, and optical shrinks.
This set of files complements your logical netlist, most commonly in the Verilog format.
Of course, you need stream data many times throughout your design flow – it is used for everything from sign-off tool design rule checking to metal fill generation and, ultimately, your final mask data sent to your manufacturing partner. The creation of the GDSII geometry data, then, is probably second nature.
What about the myriad text labels which must be present in the stream data to identify the port and net names referenced in your CDL netlist? How do you create all these text objects in the database, include them in your GDS output, and ensure that they are accurate and up to date with your design objects?
Allegro Package Designer offers the Display Pin Text command in the Manufacture menu. This go-to staple in the APD Plus editor gives you total control over more than the labels created and their content – it also allows you to describe where they are placed (class, subclass, and level of hierarchy).
However, as shown above, the price of that control is complexity. Any labels you can imagine may be created and managed through this interface. LVS, though, requires very specific labels to be placed at the top level of the design hierarchy and at precise locations relative to the pins of your components.
Once you have defined all your required text labels, you can keep them up to date easily using the Refresh Existing command, found adjacent to the display pin text command in the menu:
Run this at any time. All text labels created with the display pin text command store their configuration parameters, allowing them to check for changes in the design compared to their displayed text values. The refresh command will cycle through all your pin text labels across the breadth of your design and update them based on physical and logical design changes.
As mentioned above, LVS has specific requirements for labels it needs. These must match the descriptions in the CDL netlist that is generated for a smooth, problem-free extraction and analysis. They must appear at the top level of the GDS hierarchy. With your Silicon Layout option license and the most recent release 17.4 HotFix, you will see an additional menu item in the pin text menu to streamline this process.
Run this command after you configure your CDL netlist form and parameters. It will not only create the LVS labels which match the CDL netlist values but it will also create the manufacturing-class layers that they belong on with names you can reference in your stream out layer conversion file.
Layers will be added/removed as needed based on those layers in your design which have pins to be included in the netlist. If you rename your bottom layer from BOT_COND to BASE, trust that the tool will account for this and update your layer names for you. Add a connector component with pins on M2? That layer will be added to make room for its net and port labels when you next generate your LVS labels.
Preventing inaccurate labels that lead to false error reports from your LVS tool will save you time and frustration as you approach your tape-out deadlines!
The time’s come to create your GDS and CDL data to run through your LVS tool against your schematic golden netlist. Make sure to follow this brief checklist to get perfect data the very first time:
Run Si Layout – CDL Netlist Out… to configure and generate your LVS physical netlist.
Run Manufacture – Documentation – Display Pin Text – Auto Generate LVS Labels to create all labels referenced in your netlist from step #1.
Verify that the NET and PORT labels created in step #2 exist properly in your stream conversion file.
Run the Si Layout – PVS LVS… command to generate the GDS file in one-step, link it with your front-end schematic netlist, and run the LVS process on your selected Linux host machine.
To help remind yourself, consider making this a step in your design workflow. For more information on defining and using workflows, see the documentation and examples in your installation (or ask, and I can go over things here in the coming weeks)! A good reminder will save you aggravation at crucial, stressful times.