Get email delivery of the Cadence blog featured here
As designs get more complicated, package substrates are seeing more silicon-driven rules and structures. Substrate styles like fan-out wafer level packaging (FOWLP) and elements such as through-silicon vias (TSVs) being injected into the package layout engineer’s day-to-day existence come with rules and requirements that govern their construction. More often, these days, we are seeing strict requirements when it comes to metal density across a layer and between layers for this very reason.
It has long been the case, for instance, that you want to avoid having degassing holes in adjacent layers overlapping. This makes sense, since if they were all at the same place, as more layers are added, that area would have less material. Offsetting layer pairs provides more consistent metal coverage across layers when the entire layer stack is considered.
Today, as geometries shrink, and package substrates look ever more like silicon, we are seeing an increasing push for metal balancing across one design layer, with rules about the percentage of metal coverage needed in every region and the max difference in coverage between adjacent regions.
To keep you productive in designing these advanced node substrates, see how Cadence® SiP Layout integrates tools and functions tailored to the production of these designs. Read on, as we look at speeding your closure on complex rules with the Advanced WLP option license. I think you’ll be pleasantly surprised by how much we can help you tackle these difficult rules directly within the layout tool.
Before you begin the task of balancing your design’s metal, there are some check boxes you probably want to fill out. First, it just makes sense that you should be finished routing your design – if you’re going to be making changes and adding routing, you’re going to change the amount of metal in all the areas of the design. Why try to balance things before you even know how much metal you have for signal connections? Second, you best know the rules for the density calculations – what is the size of each region to be considered, how far do you step between regions during calculations, and what is the min/max coverage allowed? These and other rules are critical; you can’t meet a rule you don’t understand!
Once you have this information, the Advanced WLP – Metal Density Scan tool will turn those rules into a map of violating regions. It’s a complicated form, as you’ll see below, but don't be overwhelmed. We’ll walk you through the basics.
The most critical parts of this form will be driven by your manufacturing partner. If their rules specify values in absolute measurements or in percentages of the substrate dimensions, you’ll need to pick the appropriate scan partitioning mode. Then, you can enter the values for the scan step and region dimensions for each layer, as well as the coverage requirements.
A simple report of this information would be cumbersome to attempt to map back to your design (Row 4, column 5 isn’t that easy for me to find, I don’t know about you!), so the results will be placed on a manufacturing class layer. These will show the regions as squares, which can be colored to tell you what rule was violated. Because these squares are right where the actual problem is, knowing where fixes are needed is much easier.
You’ll notice one more thing in the picture above. The soldermask layers. Since it is possible that the foundry may place restrictions on the amount of soldermask coverage, it is included here as well – though these are not, strictly speaking, conductor layers.
Layers can be turned on or off as specified. If you have layers which don’t need to be checked, do yourself a favor and turn them off in the first column. These are expensive checks to run; it’s not recommended to run them where it’s unnecessary.
The PVS Metal fill command (like the others in this post, available with the Advanced WLP license option) is found in the same menu. To make full use of the high-performance metal fill generation, you will also need a license of PVS. Of course, if you are designing substrates that will go to manufacturing using the GDSII format, and are subjected to these complex balancing requirements, having a formal sign-off tool like PVS is practically a requirement.
What happens when you run the PVS Metal Fill command, the interface for which is below? By default, the tool performs things in three phases. First, it writes out the metal for the layers that need balancing to a GDSII file. This file is consumed by the PVS interface along with the rules file (may be provided by your manufacturing partner) and processed to add any necessary thieving elements and write out an updated GDSII file. This is then read back in by SIP with the thieving elements added into the design.
When you are using PVS to generate your metal fill elements, it is a good idea to import them back into your SiP database on a non-conductor layer. Why is that? Three very important reasons:
You don’t typically want to see these elements if you’re making routing changes to your design. Like a dynamic shape, the metal fill should adapt to your routing, not vice versa.
Not displaying these millions of elements will greatly improve the on-screen rendering performance. By being on a non-conductor layer, they will never be assigned to a real signal net and considered in etch calculations, DRC spacing checks, etc., either.
Should you make changes, you will want to regenerate the fill pattern again. Keeping these elements on a different layer allows you to use one stream out layer conversion file to go to PVS (without the fill elements) while a second conversion file is used to go to manufacturing and maps the conductor layer and fill layer to the same layer in the final file.
Should you not have a license of PVS with which to run the PVS Metal Fill, do not despair! You’re far from out of luck! The Advanced WLP – Metal Fill command is an advanced take on the typical thieving process, geared towards this type of design and the very high count of objects expected to be created. For that reason, you’ll see the tool offers many additional options (see below).
While it works like the standard thieving tool, the extra features add controls needed to meet the rules your manufacturing partner provides – and, of course, allows the resulting objects to be placed on a non-conductor layer.
The biggest difference is that the PVS tool will only add metal until you are within the rule specification’s required coverage. The Metal Fill command, on the other hand, will fill the area you’ve defined with as much metal as is legal. This is an important reason to consider the PVS flow, instead!
Using these commands, you can get your metal density in spec if the need is to add metal. What if you have too much metal in an area, and need to remove some? You can achieve this through the SiP tools as well.
The main contributors of metal will typically be pads and filled plane shapes. Routing traces, while adding to the coverage, are crucial to the design and aren’t normally modified. For shapes, SiP offers the shape degassing tool while for large metal pads, the pad degassing tool fills a similar role.
The degassing tool will add holes in a filled shape much the same way that PVS or the thieving command adds metal in empty areas of the design. Using a host of rules regarding adjacent-layer overlapping of holes, hole shape and spacing, angle of the pattern, and more, you can create these hole patterns in your shapes once routing is completed (or refresh them with a button push after design changes are made on a layer).
For most designs, there will be two sets of patterns for alternating layers. If the first layer has 50 um square holes with 100 um spacing, then the next layer will place its hole pattern offset from this to have the pads in the middle of the filled areas between the holes above. This acts to ensure uniform metal coverage and thickness across the complete layer stack-up.
Achieve this by configuring your pattern and then degassing all even layers. In a second pass, modify the pattern’s origin point and apply to the odd layers. Depending on the density requirements and complexity of your shape outlines, you may find you want to specify additional patterns of holes on layers. Commonly, one starts with the largest hole size and steps down with each pass. This will minimize the number of holes in the shape while providing optimal density.
If large pads exist on one or more design layers, you may need to run the pad degassing tool as well. This allows patterns of holes to be defined for the pad metal. These will be cut out of the pad itself, but also traces or shapes entering the pad (otherwise, metal density wouldn’t be reduced!).
A final consideration here. With the metal imported from PVS, we recommend placing geometries on a non-conductor layer for display performance and other reasons. With degassing, the approach is slightly different. Holes or voids MUST be associated with a specific filled metal shape. They cannot exist outside of one, so these holes are not placed on a non-conductor layer. Instead, you are given the option to defer their generation. By doing this, your patterns are stored on the shape, and when needed, the holes are automatically added to the shape. This happens when going to the analysis tools for profiling, during metal density calculations, or on export to GDSII.
We’ve shown two tools to add metal and two tools to remove it, plus a command to measure where you’re at. All the building blocks to meet the tightest density rules out there are at your fingertips. The best way to put them together on your latest advanced packaging design node, however, is up to you. Should you have requests and ideas for streamlining the entire flow, allowing you to get to closure faster, get in touch with us. We are here to help – and help may mean new features and enhancements, help to optimize your flow, or anything in between.