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Netlists. Everyone needs them! But what you are using your netlist for can have a significant influence on just what KIND of netlist you want. Fortunately, the Cadence® SiP tools offer formats for just about every situation you might run into, from initial design startup to manufacturing validation. Read on to hear about some of the options you have and design milestones they were developed to simplify.
Do you leverage a front-end schematic tool for managing the logical aspects of your design? Perhaps you use Capture or Design HDL. All of these can be read into your layout with the File – Import – Logic / Netlist command. Simply point the tool at the directory containing the netlist files and hit go.
Of course, with this flow, you need a mechanism to 'forward' annotate any changes you make in the physical layout back to the schematic. The File – Export menu has a matching command to go in the opposite direction.
In this flow, it is a good idea to take advantage of the Constraint Manager flow options. By doing so, your constraints flow both directions as well, keeping all engineers involved in the design flow in sync at all times. Just what you need for your complicated designs where things are evolving at all levels throughout the process.
Many of our readers may work for companies who have internal tools which help them generate, manage, manipulate, or validate their netlists. In this case, the third-party netlist format, which is a simple text file format that has been widely used for many years, can be the go-to. Its support for conveying net assignments as well as properties at various object levels makes it versatile while remaining easy to parse for almost anyone.
Since there are no options when exporting this format from your layout design, it has a separate command under the Export menu. Importing is done through the Other tab of the Import Logic / Netlist command, giving you consistent access to many of the same options for managing component placement, fanout updates, etc.
These are the most common formats used today. One will almost certainly be in use by your team today. But, what about more specialized formats?
If you want to read a netlist, looking at the files meant to communicate between tools isn’t ideal. Personally, I can understand data much faster in a spreadsheet format. Keeping with this, SiP offers two types of spreadsheet formats: a CSV format, the simplest to write for any budding programmer, and an open XML spreadsheet.
The XML spreadsheet is enhanced with colors matching the assigned net colors from your layout, giving an additional mechanism for finding things. This makes it particularly useful during design reviews. Take a look at a partial example below. This spreadsheet is separated into three sections. On the left are the IO (BGAs, normally) components. In the middle, the ICs (Dies), and to the right are any discrete components present.
By organizing things in this manner, you can see the most data possible on screen at a time. If there are an unequal number of pins of each component type, the next net will begin on a fresh line spread across all categories.
And, should you be looking for other spreadsheet-style views, Ball Map spreadsheets for individual components can be useful as well. These we talked about back in June (IC Packagers: A Classic Revisited - Ball Map Spreadsheets), if you recall. While they don’t convey the entire design netlist for your package, they are highly useful when dealing with the interface between the package and the next level – whether down to the PCB or up into one of the die components.
Using a formal verification tool such as Cadence’s Pegasus Verification System or Physical Verification System requires specialized netlist formats from your package design tool. Because these tools run against GDSII files, they rely on the CDL netlist format for conveying the design intent.
Thankfully, if you’re using these tools, you need only look as far as the Advanced WLP option and menu within SiP. Here, you’ll find a comprehensive CDL netlist generation tool, which can auto-generate any required resistor elements and values, synchronizing this information with the GDSII data that will be paired with it to send to the PVS engine.
While the image above may look complicated, it is not. The tool will help you by placing text labels, where necessary, in the design to identify elements when the GDSII file is output. Because the format of these labels may differ from user to user, giving you the choice ensures that you can establish your design flow here and not need to modify any rules or checks in the verification tool.
These are not all the formats available to you from within SiP. Should you have need of it, Verilog may be exported. BGA and Die text files, as mentioned earlier, can convey the netlist for individual components. SKILL allows you to create custom-formatted outputs, whether in plain text, CSV, or XML style, to read into your internal or third-party tools.
Never let the netlist be a source of concern for you again! If you’re unsure which format is best for your situation, or if you need help reading your team’s netlist format into the tool with SKILL, reach out to your Cadence customer support team for help. That’s what we are here for!