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Have you ever needed to build a component with a custom, complex pin pattern? Have you ever wanted to do so within the context of the substrate you’re working on (or, for that matter, needed to build a custom package based on a set of dies you need packaged)?
You might not realize it, but you can do this within the SiP Layout and Allegro Package Designer L environments. There is no need to first bring in a base pin pattern, or even to generate a basic die or BGA with the generators. Make full use of the symbol edit application mode to create an empty component and start adding pins to it within the full context of the surrounding layout elements that it will interface with.
To learn more about how to do this in your current 16.6 software, continue reading. You might find some interesting ways to save yourself time and streamline your design flow.
Co-design is a fact of everyday life these days. Whether you are co-designing a package with the PCB it will be mounted to, or a die within its host package, the need to optimize the two modules to minimize cost and maximize performance is one that we all face.
But, there are many scenarios where you may not be (or may not be ready/able) to start with full-blown co-design. Perhaps the IC design doesn’t yet have the LEF libraries available. Or maybe the PCB design is not yet begun. What if you’re doing a feasibility study and want to decide what the minimum pin pitch requirements are to get the smallest possible flip-chip die size that can still be escaped in a 2-layer package? There are many reasons you might want to start optimizing a component with little or no up-front information.
Enter the symbol edit application mode. Go ahead. That’s a suggestion, not just an introduction! From here, if you RMB on an empty area of the canvas, you’ll notice an option in there called “Add Component”, which, if you click on it, opens the UI shown below in your options tab:
That’s all you need to define your empty component. Give it a reference designator and a part name for the symbol, tell the tool what kind of component you’re adding, and give it some basic physical information—the size, layer, and (if you’re making a die) the attachment type and orientation. When you’re happy, click the create option, and the component will be instantiated into the drawing.
What good is a component without pins? Fortunately, you can start adding those to your component right away. The application mode gives you a wealth of options. Some you’ve seen before, and others you may not have.
Because we’re defining a standard part here, not a co-design object, any new die component will be locked by default in the tool. This is to prevent unintended edits to the component and symbol through commands like move, copy, or delete (you don’t want to spin the boundary of your die around and cause manufacturing DRC errors to be missed!). BGA components don’t get this flag by default, since the BGA is the substrate you’re designing. Either remove the locked property from your new die component or consider setting either the “icp_disable_auto_symbol_lock” or “symed_allow_locked_comp_edits” variables in your user preferences. The first will not lock the objects at all, while the second will prevent commands like the move and copy tools from changing your symbol while allowing you to make specific edits to it via the symbol edit application mode.
Before you begin adding pins, consider setting up your pin placement and pin numbering settings. These, respectively, control where pins can be placed (staggered or not, the pitch, distance from the edge of the component, and so forth) and how they are numbered by the system (basic 1, 2, 3 as you add them? Or maybe you want a spiral or alpha numeric pattern). RMB on the component and choose the “Pin Pitch Settings” and “Pin Numbering Settings”. If you know you have different regions with distinct requirements, make use of the “Add Grid” option to define those now, or you can come back and add them later.
For the most basic of flows, the next step will involve the Add Pins command, still in the RMB option when you select your component. Here, you can choose to add pins one at a time or by window. You can add more complex arrangements like rings, matrices, and even rows of pins that increase in pitch as you move out from the middle—perfect for your wire bond dies. If you have a pattern that you know is escapable already, bring that in from your favorite spreadsheet or text file.
If, on the other hand, you have been experimenting using the router already to find ideal placement for pins using vias connected to your clines and shapes, you can convert those vias directly into pins with the RMB option “Convert Vias to Pins” item. This will take those vias and create a pin for each using the same padstack, rotation, and placement information. It will even preserve the net for you. Of course, if you have defined a pin pitch to snap to, when you convert your vias, the pins will be snapped onto grid, making sure that things line up cleanly.
Oh no! Your initial estimate for the size of your component was off. Maybe it is too small. Or, maybe, it’s far too big—if that’s the case, a lottery ticket purchase may be in order on your way home, as it seems to be your lucky day. You can adjust the size through the application mode, as well. Just select the component and select the Edit Boundary option. This will even allow you to select a complex shape outline with notches if you have cause for that.
From there, you can finish off your component by adding keepouts, specifying the bump or ball geometry if this is a flip-chip or a BGA, or moving the origin of the symbol to a specific pin’s location, the center, or one of the corners. And, when you’re finished, you can save all your work to a library object for later reuse. All without having left the layout canvas once!
Cadence offers some very powerful tools for doing feasibility, planning, and prototyping. Here, we have looked at the flow when you need to develop a component within the context of a package, complete with the ability to do detailed routing tradeoffs, escape routing checks, and the like.
But, there are also other tools. OrbitIO, for instance, will allow you to very quickly plan and prototype your entire system—board, package, and chip. Optimize your nets at each level of hierarchy and then export those results to your PCB, package, and IC layout tools.
How do you prototype within Cadence? Is there something that could be added to your favorite design tool to make your flow faster and easier, so you can get the answers you need to decide whether to proceed with a project? Will it be profitable? Or will it even be possible? Share your ideas with us, either in the comments or by contacting your Cadence support representative. We’d love to hear your ideas. Making you successful is our goal!