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When a change comes in from your IC design partner, it can be met with trepidation. How drastic is the change? What impact will it have on the package routing and (potentially) even the layer count needed to fan out the die? Will the bond finger tiers need to be redone to keep wires from crossing and raising the unit cost with the need for more extensive manual checking?
The simple fact is that ECOs are a part of our daily job. There’s no avoiding them. Instead, embrace the changes as a part of your flow and you will find the flow that much easier. How can you do that, do you say? Read on, as we cover some of the considerations and the ideal solutions for bringing a change in from the mundane to the extreme.
First off, most ECOs coming into package substrates will affect the die components. The BGA or package interface is typically more under control of the package designers themselves. While it will change, those changes are driven by you, for your benefit, unless the PCB on which you will mount the finished package changes extensively.
This is important! DO NOT delete/unplace the component you are trying to update! Why, you ask? Because if you do that, the system loses the knowledge of what the pin to escape routing was. This is key to getting the cleanest routing adjustments when you bring the ECO modifications in.
Below, we can see the options that you’d find when processing an update through any of the die import mechanisms in Allegro® Package Designer Plus. For wire bond dies, the options are a little bit different (you’re processing 3D bond wire connections to fingers and other dies instead of vias and traces), but the mapping options to pins remain consistent.
I think the most common option here would be to reconnect the etch by net name. If you swap the nets on two pins of the die, you will normally want those connections to swap, too. If you can, though, update by pin name or number, or even to the closest pin location to the escape routing terminus. This is ideal in scenarios where the BGA is fully in your control – the net assignment can be pushed out through the routing all the way to the BGA ball and plating bar pin. In these cases, it is possible to avoid any change to the package routing… of course, you’re pushing the problem out to the PCB designer.
What happens to the routing based on pin movements? Look below, where I’ve shifted the pins as part of the ECO. Die replacement takes this and stretches the final segment of the traces to the new pin location. Vias, via stacks, and structures, and moved to the new pin origin. Instead, the first cline segment that connects to the end of the via or structure is stretched.
This is important if those structures are key to proper escape routing. The structure remains unchanged, still perfectly aligned to the center of the pin. As part of a differential pair, both structures will offset the same way, maintaining proper alignment.
While I’ve accentuated the changes above for clearer visibility, if the pin shift is subtle, the via might still overlap the pin, maintaining the signal connectivity. However, not being centered on the pin can lead to manufacturing or yield issues. It’s better as much as possible to keep things optimally aligned. Let the system manage this for you and you don’t need to concern yourself. One less thing off your personal to-do list (mine’s bigger than I can get done, so I will always take a freebie or two!) is not something to toss aside.
In the event you forget some of the above (or are worried that things are misaligned due to some other step in your flow), the Cadence tools offer you a check – with the ability to auto fix – of via to pin alignments.
Under the Tools menu, find the Package Design Integrity command. There, under the Manufacturing category, you’ll find the Via-Pin Alignment check (there are also via stack alignment, redundant padstacks, and many other checks that will preemptively catch issues). Use this check any time during your design process to set your mind at ease as to any potential problems waiting to happen.
The concerns for different types of ECOs will vary. If you have a need for different behavior than offered today, please reach out to your customer service team. Explain your needs, and we will do everything we can to help you out with that.
Should you need to add an integrity check like the ones mentioned earlier, you can add your own custom checks, too. Search for the axlPackageDesignCheck series of functions in the SKILL function documentation of your installation hierarchy.
At the end of the day, the most important thing to remember is that you’re not in this alone. We’re here to help!