IC Packaging and SiP Blogs

I could doubtless extend this series all year long, covering the important updates, improvements, and completely new functionality that is continually being added to the Allegro^® Package Designer product. This will be my last before we shift back to more traditional best practices and similar discussions next week. Let’s dive back in and make your experience with the Allegro layout tools faster and more efficient with new goodies!

Lock Toolbars to Prevent Accidental UI Reconfiguring 

The top (and, for some, side) toolbar icons are a mainstay in the Allegro layout tools. Shown in dark theme in the image below, the vertical lines of dots denote the start of individual named toolbars. When you click and drag one of these, it allows you to reposition the toolbars to your liking.

While this gives you flexibility, it also raises the chance that you can unintentionally click one of these anchors. Then, a quick mouse move can have all your toolbars rushing to adapt to the updated ordering. Oops! Now, you can prevent this from happening. Once you have established your go-to arrangement of icons, you can lock them by setting the allegro_lock_toolbars environment variable. As soon as this is toggled, the toolbars will lock in place and not allow any inadvertent edits.

The easiest visual cue to see this is the disappearance of the anchor bars, as you can see below. Of course, all the opportunities for custom icons we discussed with 17.4 QIR1 still apply. When your own icons are mixed into the Cadence^® standard icons, you’ll have speedy access to every command you want any time you want to use it.

One additional tweak you may have noticed: the old floppy disk save icon is back at your request!

Package Integrity Checks for Dielectric Opening Style Padstacks 

The Package Design Integrity Checks interface provides ways to quickly locate logical or design errors in your substrate that may not be database errors. Instead, they are unintended constructs that you want to be sure to correct prior to going to manufacturing.

With many of you designing silicon interposers, or just opting to use named dielectric layers with pads on them to represent the drill shapes in your padstacks, it becomes critical that you validate your connections move between adjacent routing layers as intended.

For this reason, look to enable the logic group of integrity checks by setting the packinteg_logic_checks environment variable, below:

Once set and the tool restarted, you will see an additional folder in the integrity checks GUI:

The four rules here combine to provide a comprehensive scan of the database for errors that are not detected through the traditional shorting and net path tracing in the database, which assumes a drill hole in the padstack based vertical connection method.

These checks can isolate and report many situations, including:

• Padstacks that start or end with a dielectric opening, leading to shorts to adjacent metal layers.

• Padstacks with a missing dielectric opening anywhere in the span, implying a broken connection path.

• Broken connections caused by missing conductor (metal) pads between named dielectrics.

• Routing or other objects on named dielectric layers. These are very dangerous! If you will be exporting the dielectric layer with the via pads defining the layer transitions, should you unintentionally add a shape, cline, line, or other objects to that dielectric layer, you may be creating an unnoticed short between the layers above and below. Be careful!

Named dielectrics have many uses, but they do come with some added risks that you need to manage. The flexibility of the Allegro tools means you can design nearly any substrate imaginable. Stray too far from the traditional flows may mean leveraging the integrity checks or even your own Ravel rules to check and validate your design prior to manufacturing.  

Configuring Nets for Pin Extension Macros

We first started talking about pin extensions in October of last year. Back then, they were first being introduced. Then, we discussed briefly how you could assign text labels in the GDSII file describing the pin extension to indicate that certain objects (net branches) belonged on target power and ground nets.

With HotFix 13, you are ready to take advantage of this exciting capability. I’m excited to tell you to look under the Route - Structures menu to find the Setup Net Mapping command.

This command should be run after you bring in your pin extension structures. The UI which comes up (shown below) will list all the structure branch net labels found in pin extension structures currently loaded in the database in addition to the structures which reference each branch name.

All designs will not have the same net names; in some designs, it may even be desirable to map multiple branches to the same net name. Use descriptive branch names when designing your pin extensions and your design teams will be able to rapidly determine the intended net to use.   

After you assign a net to each unique structure branch, any time you place a pin that references one of those extensions, these branch elements will be pushed to the appropriate power or ground net. Later, if you need to change the net mapping, open this form again and change things. All extensions instantiated in the design will update automatically. Of course, if you’ve already routed out from the pin extension objects, you might get DRCs. Those DRC markers provide a very useful visual indicator of update work to be done to complete the net changes.

What’s Your Favorite New Feature?

We’d love to hear what you think. This is a small piece of the new functionality found in 17.4 HotFix 13 of Allegro Package Designer Plus. Are there other dynamic updates you would delay during expensive, cloaked actions? Other structure types that would benefit from the power/ground labeling to automate net propagation? Let us know so that we can work with you to keep making the tool use models simpler to use while being more powerful.