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It may surprise some of you, but I often receive databases in which the power and ground nets are not properly identified. Many times, I get these with questions about slow performance during editing actions in the design or a basic confusion of why the net name isn’t shown in a pull-down to be selected in a command.
For any Allegro layout product to truly understand that a net is intended for use as a DC net, certain attributes need to exist. Others should exist and are recommended, but they aren’t formally required for most parts of the system to behave properly.
The only *requirement* for a net to be classified as power or ground is that the net has the VOLTAGE property on it. This property takes a value which is the voltage level. A value of zero volts means the net is a ground net, while a non-zero value like 3.0v or 1.5v indicates a power net. Cadence also strongly suggests setting the RATSNEST_SCHEDULE property with a value of POWER_AND_GROUND and/or the NO_RAT property. We’ll touch on why these are so important in just a few minutes.
The properties may be added through multiple interfaces. If you have a front-end schematic design, having the net there and having it classified as a DC net with its proper voltage level will allow that property to flow into the back-end layout database when you push the netlist across. This is the recommended flow, of course, since it will ensure the net not only identifies as DC but is the right type and right voltage as well.
If you aren’t using a front-end tool (and not all packages use them!), but your nets are instead coming in through Die/BGA text files, XDA co-design die definitions, or another format, consider setting the power and ground regular expression environment variables:
POWER_NET_REGEX: Defines all the regular expressions that are used to identify power nets. Any net name matching one of these regular expressions, when added to the design, will get the VOLTAGE property (with a default 1.5v value) along with the NO_RAT and RATSNEST_SCHEDULE properties.
GROUND_NET_REGEX: Defines all the regular expressions that are used to identify ground nets. Any net name matching one of these regular expressions will get the same properties like the power nets above, but with a voltage value of 0.0v.
Both variables can have multiple regular expressions separated from each other with a | (a vertical bar) character. Just keep in mind that the voltage value is a default. These should be configured with the correct voltage for each design and net.
As many teams have a naming convention for their power and ground nets, the regular expression settings above may serve as both an auto-identifier when nets are created, but also as a net (pardon my pun) for catching nets defined in your schematic or elsewhere but missed their DC properties.
The pin use assigned to the pin of a component may also be used to drive its intended usage. The pin use can help to drive the correct class of nets being assigned to the pins, for instance, and pins with a power or ground pin use may, if you want them to, be created without logical pin names. This means they won’t show up in the standard list of signal pins in function pin reports or in the front end.
More people are turning away from leveraging this to keep the DC pins out of their schematics, however, instead of using the ability to visualize the pins (and breaking the components across multiple pages) to heighten planning measures to ensure adequate power and ground supply.
Regardless of whether you opt to use the POWER and GROUND pin uses on your pins instead of BIDIRECTIONAL, IN, and OUT, the net’s classification is what will primarily drive functionality in the tool. After all, if you ponder it, what does it mean to say that a pin is a power pin if the voltage level it supplies is unknown?
For this reason, we suggest focusing more on classifying your nets. Pins can determine their usage based on the net they are assigned to. If you are working to co-design a component interface with your IC design team, or your BGA with the PCB group, net swaps on the pins during the flow may make the pin uses difficult to maintain an accurate grasp of.
At the end of the design, when all assignments are fixed and you’re locking down this design, update the final pin uses based on the net assignments should you like. When you go to create a library part from your BGA, this will allow the PCB designer a better understanding of what a pin’s purpose is.
This can be done with the auto-assign pin use command, interface shown above, found in the Logic menu. The command lets you pick one of your components where the pin uses are configured (your die, typically, if it drove the connectivity on the BGA) and map the pins on the other side based on the final net mappings between the components.
If you haven’t set the regular expressions before you created your nets, are bringing older designs forward to modern database revisions, or simply work with many different teams who all use different naming conventions, is there still a way to find nets which should be classified as power or ground but, currently, are not?
Yes! From the Tools - Package Integrity Check command, look for the Unidentified Voltage Nets check in the general category. Running this in non-fixing mode will provide you a list of all the nets that, based on pin count, are probably intended as DC nets. Running in fixing mode will add the set of properties mentioned previously to all these nets for you. You can find the full description for this check below:
Should you prefer a more manual approach, the Identify DC Nets command, under the Logic menu, will allow you to do wildcard-based searches of nets by name so that you can add voltage properties yourself.
When your nets are all classified accurately, you’ll find that the Allegro system is faster and more efficient when dealing with these nets. Likewise, when you start adding shapes and other typically-DC-net-based features to the design, the focused set of nets will list only those you should be selecting from, making it simpler to find the right name. See here, in the add rectangle command:
Most important of all (if you ask me), you will get more accurate results and output. When you go to perform signal, power, or thermal integrity analysis, identification of these nets is critical. Similarly, when generating a board level component for the PCB design team, any pin delay measurements will not attempt to provide this information, which makes no real sense, for the voltage nets.