IC Packaging and SiP Blogs

As promised, we’re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro^® Package Designer Plus community. Without further ado, then, let’s get to the good stuff!

Flip-Chip Pillar Definitions

The Allegro Package Designer tools have supported a pillar attachment type for pins since the Symbol Edit Application Mode was first introduced to the tool. But the 17.4 QIR2 release marks the first official update where pillars may be accurately profiled in terms of size, shape, and material.

As shown above, a pin designated as a pillar attachment gets a different view in the bump/ball parameters UI. Pick a reference layer that identifies the 2D shape of the pillar (rectangular, typically). Then, add the height and material and you’re finished! It’s really that easy! By selecting a layer with geometries representing the pillar, you gain access to the easy definition of a range of shapes for the pillars from simple circles and squares to n-sided polygons and even custom shapes.

I would be remiss if I didn’t mention the corresponding change for bumps and balls, too. To keep alignment between the two interfaces, and to streamline the data synchronization with the SI tools, the ball interface has also changed from specifying the electrical conductivity for the bumps to instead selecting the material. This way, the material information can flow seamlessly into the Sigrity environment for analysis.

Now, if material characteristics need to be updated or corrected, this can be performed in the common materials file and the parameters will flow into all the databases that need that information.

Package Overlay Views for Standard Dies and Packages 

In November 2020, we touched on the package overlay view that could be generated for your co-design dies to facilitate collaboration with your IC design team. With HotFix 13, you are now able to generate this overlay for any die or package component in the substrate.

What has changed to allow this for standard die components? You, our design community! With the increasing number of 3DIC designs with interposers, multiple dies, and even package on package layouts, seeing this reference data (and being able to orient it with respect to a different component) is becoming increasingly important.

Of course, this is especially important when talking about the context of the entire system. The IC design still benefits from this view, but the file can also serve as a reference for orienting the different die pin patterns as you combine things into a top-level view of the larger world of your design.

The view from the package designer’s perspective (pick your BGA from the components list) is particularly useful for an SI engineer who is assembling all the different fabrics together for analysis runs.

And, being XML, you can even write your own tools to extract the geometries from this file for displaying or reference in your own internal tools, should you need it, without reconstructing things from the extract output or writing your own SKILL tools to pull out the data you need.

PVS Interface Consolidation 

The Allegro Package Designer’s interface to PVS has seen some significant rework in terms of use model and capabilities. This will continue as we move forward and a growing number of you rely on the formal verification tool before you head to manufacturing.

In 17.4 HotFix12 and earlier, there were three individual interfaces to the PVS tool – for physical DRC, LVS, and Metal Fill. Now, these have been combined into a single interface for easier configuration. You can see this below:

All your existing scripts from the old commands will continue to work, but you may want to gradually record these fresh with the new dialog to take advantage of the new capabilities. What has changed, you ask? Let’s talk about a few of the biggest improvements:

1. For those accessing PVS from a Windows machine, your Linux setup will be saved to your pcbenv/env file. Most users tend to have a single machine or LSF farm that they use. This has been done to prevent you from having to enter the same information multiple times.

2. All three modes – Physical DRC, Metal Fill, and LVS – allow you to provide custom arguments to be included on the PVS command line when run. If you need specific options for your flow, enter them here.

3. When performing physical DRC runs, new filters allow you to quickly show only those rules which apply to the layer(s) you are working on. There’s still a regular expression for filtering rules by name. But, if you don’t know the names and just want to run “all the rules for the top layer of my design”, uncheck everything but TOP in the Conductors folder of the layer tree and you’re all set!

4. Support for Pegasus as well as PVS. If you have the latest and greatest of the Cadence^® verification tools, access them from your Allegro environment by configuring these in the PVS Host tab.

We believe that you’ll find this environment much easier to use, whether you are working on Windows or Linux. Cadence will continue to improve this interface with each release based on your feedback, too, so be sure to share your likes (and dislikes!) with your Cadence customer support experts!

Is there More? 

You’ll have to come back next week to find out!