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Welcome to a brand-new year, everyone! As we welcome in 2021, we also welcome the next major update to the 17.4 Allegro platform release in the form of QIR2 (hotfix 13). These new updates are exciting for many reasons. Of course, they bring bug fixes, which are critical. Alongside those, you will also find new performance improvements and new features.
In terms of IC Package and silicon interposer design with Allegro® Package Designer Plus, let’s cover those that are going to have the largest impact on your design flow and productivity.
Some of you may have used the grid-based fast pour mode in 17.2 and 17.4 which replaced the older rough mode. With grid-based pour, your shapes were segmented into regions. By doing this, any change made would impact only the local areas of your large planes, no matter the type of change or its location. This could offer significant improvements to voiding performance over the artwork-ready smooth mode.
It came at a cost, however. The boundary areas between the grid regions would not be an accurate representation of the final metal. Meaning you couldn’t use these results for SI analysis, among other things. You might also see areas of the shape that would be suppressed in the final artwork due to being under the minimum shape area.
With hotfix 13, this has changed. While the mode’s name remains “Fast”, the gridded system for localizing edits has been replaced with a more comprehensive repair process. This is much closer to the final smooth shapes that go to manufacturing, differing primarily where individual vertices are subject to frequent updates.
The Fast mode has been proven to be upwards of 50x faster than smooth mode with very similar accuracy. It does not suffer the weaknesses around minimum shape area and island suppression that its predecessor did.
Enable fast from the global dynamic shape parameters form, as shown above, and take advantage of very close to final artwork shapes at record-setting performance.
While we’re talking about shapes, I would be remiss if I didn’t talk about this thrilling new feature. One of the most frequent requests from all of you has been the ability to control the dynamic shape defaults at the layer level.
This allows for designers to have global defaults but also defaults that apply (by default; pardon the pun) whenever a new shape is added on a given *layer* of the design. This GREATLY reduces the number of shape instance overrides you need to apply and manage in your design.
Above, you can see the UI. This looks very much like the global and instance parameter pages, with the largest difference being the Layer pulldown and the Copy To Layers buttons. Not immediately obvious, however, is that the shape instance override colors apply in this form as well. Interested in what layer(s) have parameters different from the top-level global settings? You’ll see everything highlighted in blue – including the tabs. This lets you confirm, at a glance, that there are no clearance overrides on a given layer without even needing to click the Clearances tab.
Layer-based parameters allow you to put the different manufacturing configurations at the layer level where they belong. Do your plane layers have different minimum shape widths than your routing layers? Maybe you have silicon layers for an interposer above the laminate layers for the traditional package substrate. Whatever the reason, place the unique settings here.
Lest you worry, the shape report has been updated accordingly. For each layer, see the settings overridden from the global defaults. With the full hierarchy of overrides visible in this report, quickly get a comprehensive detail of where shapes have unique settings.
The die text and BGA text import interfaces are two of the most heavily used when it comes to bringing your parts into the design. Because the text files are adaptable and easily editable in a spreadsheet, they can typically be written by any tool either natively or via scripting. This makes them particularly valuable for an ECO action. If you are updating a die component with a text file, you’re familiar with the die replace interface, shown below. This allows you to control how the routing connections are updated based on the changes from your IC design team or PCB partners.
With 17.4 QIR3, you’ll see the new option for mapping padstacks. This has been added in acknowledgment of the fact that the IC designer often does not know the padstack to be used for the contact pads the package substrate for a flip-chip’s bumps. These pads are frequently a different size and shape from the exposed metal on the die itself (not to mention needing soldermask openings and other package-specific geometries).
By allowing padstacks to be mapped like the routing connections, the need to modify the die text file to set the right padstack is removed. Map things during the replacement operation itself. If different designs have different landing pads for the same die, it’s still possible to use the same source text file. And, if you tuned in when we talked about pin extensions, yes, these will be applied at the same time!
This replacement interface will be applied to other flows as well. Whether it is a BGA coming in through BGA text in or elsewhere, any command which is enabled for replacement updates will present the same UI.
Are there device update flows that don’t apply the replacement interface that you think would benefit from its addition? How about being able to save replacement settings to use during any such action instead of displaying the form? Let us know how you’d further improve this flow so we can help you work even faster!
There are many more exciting improvements than covered today. Next week, join us again to learn about even more!