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As the component count increases in package/interposer designs, many more of you are turning to front-end schematic tools for managing the netlist and connectivity. When working directly inside the layout design, however, there remain many cases where it may be easy and desirable to rename one or more nets.
Whether you are correcting a misspelled name, changing names to reflect an updated net name convention within your company or team, or replacing a placeholder net with its formal name, the Allegro Package Designer tool makes this much easier than many backend layout environments out there.
How does it do this? The Logic menu of the tool contains various commands – from creating and delete net to assign net and derive assignment. To change the net name, which typically implies you do not want to change its assigned properties, net group memberships, constraints, or anything else (just its name), these commands are unsuitable. Enter the Rename Net group of commands. Want to know more? Keep on reading!
Rename Net under the Logic menu contains three different commands to enable distinct flows. Which one you need depends largely upon the reason for renaming nets (and possibly how many you’re changing).
These are available at any level of the physical layout tools. They aren’t present in the signal integrity tools for you electrical engineers, I’m sorry to say. But, let’s look at when, and how, you would normally apply them in a flow.
When you need to rename all – or many of – the nets in your design, this should be your go-to. Alternatively, if you got a list of before and after name mappings from your IC or PCB designer that you need to match to, it will make the chore far less arduous.
The Batch tool is the only one that requires external information. In this case, it comes in the form of a text file. The file is an extremely simple two-column tab-separated value file. The old names on the left, new names on the right. Whether you want to create this in Excel with macros, a text editor, or you’re fortunate enough to receive it, pick the file on disk and all your net names will be changed.
Yep. That’s seriously all there is to it. There isn’t much simpler a file format you’ll find. Even so, this can be very valuable in certain scenarios. One example I can think of is changing the names of power or ground nets. If you are changing your default net names from VSS to GND or GROUND across all your designs, this is a very efficient way to do so.
When a net name listed in the file doesn’t exist in the design, you’ll be notified, and that line of the file will be bypassed. It won’t count as an error, just an observational note. This way, you can reuse the same mapping file across many different designs.
Another common scenario can lead to the need for a template (pattern-based) net renaming. Whether you want the net names to have a unique prefix for a given revision or instance of a reusable design module or want to take an existing design and strip off said prefix strings, template renaming is the tool for the job.
With this command, you give it the strings to search and replace, or to remove entirely. See the simple UI below:
Deleting a prefix string may not be as common as substring replacement, but both are offered. In the example above, I am going to change all my ground nets, which used to be identified with the string GND, to use the full word, GROUND, instead.
The primary scenario where I’ve seen a desire to delete a prefix string so far actually comes when importing module instances into the layout. As you doubtless know, a module is given a unique instance name. And, its nets are prefixed with that instance name to separate them from the other modules and the top-level design netlist.
Removing the prefix (or converting it to something else) allows you to separate the net naming patterns from the module’s own net name.
Last, but certainly not least, there is an interactive renaming of nets. Pick a net and enter a new net name in the pop-up form that appears:
The form, when it appears, is pre-populated with the original net name. If you accidentally choose the wrong net, a quick tap of the enter key will close the form and nothing will change. But, once you verify the right net is active, type in the new name.
Hit enter and see the net name on the objects update. Browse Constraint Manager or any of the other netlist-driven tools in the tool and see the modification. It’s as easy as that. From your net via padstack list to the net-level properties, everything will be safely preserved.
I’ve avoided talking about a scenario that you no doubt are worried about. What happens if you try to rename VSS to VSS1, but VSS1 *already* exists in the design? Fear not. In this case, whether you’re in the batch, template, or interactive net rename command, you’ll be issued a choice: merge the two nets together, or provide a different (unique, this time) name.
When you merge nets together, of course, DRCs will need to recalculate, and shapes will update because the spacing constraints on the old and new nets may well be different. That is the main difference.
For those of you who have imported an IC with a set of voltage region nets that all need to combine to a single net at the package level, this merge option can be very, very powerful, indeed.
The next time you need to make changes, consider the rename net commands. They could well save you significant effort and that most valuable of all resources: time.