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Manufacturability and quality of the power and ground feeds for your package are always a big concern for all of us. When you have multiple plane layers, connecting them together with reinforcing vias is a great idea, with just one problem: how do you figure out where to put them that won't conflict with anything connected to the planes—or anything on the layers between them?
This connection can be a very time-consuming process. After placing a via where you think it can go, you may find a DRC between it and a cline three layers lower (that may not even be visible at present). This can be even further exasperating when you get your reinforcing vias placed and then need to handle an ECO change request that involves moving some routing—and therefore one or more of these vias.
How, then, do you manage this desirable step of the flow in a way that is quick and convenient? With 16.6 APD and SiP Layout from Cadence, you just need to leverage the shorting via array command! Interested in learning more? Keep reading!
This command, new to the 16.6 release of the Cadence IC Package layout products, gives you the ability to pick two plane shapes and configure parameters for defining the via array. You can find the command under the Manufacturing -> Shape Via Shorting... menu item.
Control the minimum spacing between vias in the array, clearances to other objects, and even the rotation of the vias if they are not circular pads for the connections to be established. Take a look at all your available options, shown here in a picture of the interface:
For those long-time users of APD and SiP Layout, the options here may look quite familiar to you. That's because many of the same settings are available in the shape degassing tool. Combining these two tools together actually gives you even more power! You can specify the via array parameters and, after that, define degassing holes with array parameters that place them ideally relative to the regular pattern of the reinforcing vias.
Earlier, we mentioned how tedious it can be if you need to update these vias because of an ECO order requiring substrate routing changes. With the shorting via array command, delete the vias out of the way in the areas where you are modifying routing. When you are finished, run the command again, pick the shapes, and your original settings are automatically updated to the form. A single button press will regenerate all the vias with appropriate spacing to all your new routing. Talk about saving time!
Now that you know about this helpful tool, do you have some ideas for improving its usefulness? Is there an additional constraint that you require to get your vias placed perfectly? Do you have a large number of shapes and want a batch update tool to run after your ECO changes? Perhaps there is a new constraint or package-integrity check that you would like added to verify that all these arrays are up to date (or that all layer pairs are connected with reinforcing vias). Whatever your idea, share it with your Cadence support representative and we will make sure it gets to the engineering team to consider for the next release!