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Wire bonding has been around forever. Flip-chip mounting? That’s been around for a long time as well. Every new generation of packages brings with it new technologies, challenges, and options. Copper pillars have been around for a fair time as well, but they have been seeing a growth in application the last few years, it seems.
If any of you are not yet using, but are interested in, this type of attachment, the picture below gives you a brief breakdown of the various parts and pieces involved. From the solder through the copper pillar (or post) to the underlying passivation openings on the die itself, all the important elements are shown.
You can find greater details from your manufacturing partner, clearly. While the background is important, we’re here to show you how best to use the power of the Cadence® package layout tools to design these faster, smarter, and more successfully than you would be able to anywhere else.
First up is defining your padstacks. Because a pillar has different levels of important geometries that you need to consider when doing DRC checking, how you set up the pads is crucial. The correct configuration will ensure that you get accurate spacing DRC checking as well as proper SI/PI analysis with the Sigrity tools.
Pads which you need to define/consider:
The package landing pad: This pad represents the landing area on the package substrate (or the interposer, if you’re placing this die on top of one) and should define the full size and shape of the landing pad that is on the top metal layer you connect to.
The route keepout: this pad definition, typically a two-part flash symbol, controls the entry angles for the padstack to make sure that your traces enter at the correct angles and sides of the pad for reliable pillar connectivity.
Mask layer pad(s): these pads define the geometries of the pillar itself. If there are multiple sizes and/or shapes, you can define multiple mask layer pads. These will be used for inter-layer DRC spacing checks in the layout, allow you to do pillar to pillar spacing checks and pillar to surface metal feature checks using the inter-layer DRC functionality.
Pads which should NOT be in your padstack:
Conductor layer pads representing the pillar and manufacturing layers. Including these in conductor layers can interfere with accurate display and SI/PI analysis results.
Die side pad geometry. These pads, which belong to the die itself, are automatically managed for co-design die objects. For standard dies, the die symbol itself is presumed to contain this data for reference as needed.
If you follow these simple guidelines, the rest of your flow through the tool should work consistently and reliably. How you set up your DRC checks for your pillars comes next.
The inter-layer spacing DRC checks can be used to do basic checks. In Constraint Manager, go to the Spacing workbook, Inter-Layer sheet, and spacing. Here, you get a matrix of all the layer pair combinations that you can define rules for. This is just one reason why placing your pillar definitions on a mask layer is useful.
Trim one list to just geometry layers so you can find your named mask layer and enable checks between it and the conductor and/or pads. Then, you can indicate the check type (gap, overlap, etc.) and both DRC character and text description, plus the layer you want any violation markers placed on. Depending on your specific needs, you might want the markers on the conductor layer, so you can adjust the routing, or on the inter-layer DRC layer for simpler on/off toggle when you are interested in seeing these violations.
Below is a simple example where I defined spacing rules between the pillar and the landing pads for the surrounding pillars and vias, but also a check for the pillar to any traces, shapes, and other metal on the conductor layer.
This may not be a perfect, complete definition for your spacing checks, however. You’ll notice that when you define these rules, you will also see a violation marker in the canvas between the pad and the cline that escapes from it. This is explicit because this is an inter-layer gap check.
We don’t distinguish connected objects in this case. Because the spacing is less than required, you get an error marker. While the check is correct, you may not wish to see these specific errors. How, then, do you ignore/suppress these checks while still seeing the situations that you DO care about?
Enter the next level of custom solutions: RAVEL rule checks. These rules are written by yourself, your manufacturer, or Cadence. The rules allow full customization of the inputs and outputs for your specific design needs. In the case above, your rule might suppress or ignore those elements directly connected to the pin or via pad, may ignore all same-net proximity violations, or may only worry if the metal itself is exposed through a soldermask opening. Whatever the need, a custom rule can check – or NOT check – exactly to your definition.
If you’ve never worked with RAVEL rule checks, this may be the ideal time to consider them. While we won’t get into the details here (that’s a discussion would take more time than we have here, regardless of how valuable it would be), there are experts on the Cadence team who can help you. Reach out, and the team will answer all your questions.
Identifying your padstack with the appropriate mask layers is almost, but not quite, enough. This does not provide some data that is needed by various interfaces. For instance, it does not tell the 3D Viewer how tall the bump is, nor does it tell the Sigrity tools the material (we might call them copper pillars, but they aren’t always copper!).
Do this through the symbol edit application mode. Here, you can assign data at either the component level or the individual pin level, if you have a mixture of pillar types or pad types. This is especially likely if you’re doing a two-sided die component, as we spoke a week ago.
In the form above, accessible from, with a right-click, on either the component/symbol (global setting) or pin (instance override), you can describe the height, diameter (for bumps), and conductivity of the pillars. This information is used by the Sigrity tool when modeling your connections, but also in the 3D Viewer. It’s accounted for in areas like the die stack editor when determining overall component/stack heights. If you are stacking wire bond dies on top of pillar dies, it even factors into your wire bond 3D lengths and the amount of wire you need to complete the package layout. Having accurate data here ensures that you know the cost to manufacture a single part. Don’t forget this!
NOTE: You can access the component’s bump/pillar geometry details from the Die Stack Editor as well, but only the global setting for the entire component.
In the image below, you can see an example showing some pillars sitting atop routing and shapes on a substrate layer.
With the route keepout shapes we discussed earlier defined by flash symbols, we can easily ensure that the pillars have adequate clearances from not just the shape pour in red, (for both nets), but also that the connections themselves are ideally oriented for the bump geometry.
It is not uncommon for copper pillar designers to rotate the pillars, with them facing the nearest 45-degree angle from the center of the component. This assists with thermal expansion concerns if you remember our talk about that from a few weeks ago. Using a keep out pad in this way means that every pad automatically adjusts based on the individual orientation of the pillar. No additional work needed on your part!
Should you find yourself designing a package with a copper pillar mounted die in the future, do not fear. If you need some assistance, please reach out to our experienced team of experts here with all your questions. It’s our pleasure to help you get the very most out of our tools, whether that is in terms of designer performance, quality of results, or flexibility.