Hello, everyone, and a happy new year! Last year was incredibly exciting for IC Packaging, with all the emerging options coming with silicon interposers, 3DIC innovations, and so much more. The options we are seeing continue to expand at lightning speed. Keeping up with all your choices can be a handful. Fortunately, the Cadence® Allegro® Package Designer platform has you covered for all these substrate styles and more.
Read on to learn more about what the team has been working on to help you with tasks both complex and routine to ensure that you meet your deadlines and get to market on schedule, with the best possible layouts. I, for one, am incredibly excited to see where 2022 takes us. I hope you are as well.
Routing structures are elements we talk about at least once or twice every year now. That’s because they offer so many efficiency gains versus flat routing. Complex patterns that match each other exactly are hugely important with today’s high-speed signals.
There are more benefits with structures than that though. If you grab the latest 17.4 release of Allegro® Package Designer Plus, the opportunity to define structures composed of nothing but route keepout geometries may be very, very helpful to you when implementing custom hole patterns in your shielding planes. Should you need route keepouts in very specific situations to protect high-speed routing, or if you’re attempting to create a stacked set of holes that are positioned with exact amounts of overlap to each other, a route keepout structure may be just what you need.
Or, for differential pairs and more complex, multi-net structures, using an origin reference point that is in the center of the structure instead of on a specific via or cline endpoint can make placement of arrays of structures simpler and faster to achieve. As you can see in the following image, simply turn off the option for snapping the original to a structure routing element. Then, place the origin point anywhere in the structure.
If you have a flow involving structures that could work better or be useful to others out there, let us know. We are here to make the tool as easy to use, to help you be as productive as possible.
Acute angles are a problem in any substrate design. They can lead to acid traps or opportunities for the conductive metal to peel away, potentially resulting in a broken connection. For this reason, with the latest 17.4 version, the auto-fixing tool for acute angles repairs more violations than ever. The most important addition is the ability to configure each layer individually, as shown in the graphic below:
This may seem like a small measure, but if you are designing a layout with a mixture of technologies or with varying metal width and spacing rules, this is invaluable. The length for the auto-fixer edges can also now be configured to read the DRC constraints (line to line spacing) to apply on the individual violation, ensuring that as much metal is added as is needed – and not a bit more!
Making use of the auto-fixers in the Allegro Package Designer tool can save you hours of manual effort over other flows, especially as you work to adapt to changes through ECO actions moving towards your final layout!
Everyone needs power and ground delivery. After all, nothing gets done without power. Because of this, the Allegro Package Designer Plus team has been working hard with our partners to develop a world-class power delivery planning solution.
By allowing you to plan the plane generation and groupings on each conductor layer directly alongside the via transition priorities, you can make rapid trade-offs for different options. Is an alternating power-ground layer assignment pattern going to work better for your design, or do you want to have power closer to the center of the substrate with the grounds providing additional guards near the component interfaces on the outer surface layers?
Allegro Package Designer Plus provides solutions for all styles of power planning. Whether it is a more IC Package/PCB style using power plane shapes with via patterns to get between layers, or a rail style solution often seen in the digital IC domain. The tools to develop and optimize these are all available from within the Silicon Layout option’s command set.
For help with these tools and how to use them optimally, reach out to your Cadence support representatives. They’ll be very happy to work with you to gain experience and afford you significant time savings when planning the power solution for your next design! These tools are being actively developed to meet your needs; today, you will need to enable them as early-access features as we expand them to ensure that everyone’s needs are met for their custom design styles.
With export and import access to your favorite spreadsheet tool, you can create sets of power plans and reuse them across different, similar designs. Build up a set of options and apply them to your next design to see which one works best. If you have a design with distinct regions needing different solutions (under a large die versus in the peripheral of the BGA ball pattern), the tool will even allow you to apply different patterns to different areas. In these advanced cases, combining each distinct area’s rules into a separate, helpfully named worksheet in the spreadsheet repository allows you to rapidly apply it, by name, to individual regions and keep things up to date.
When designing in silicon, many of us will be leveraging formal sign-off engines such as the Pegasus platform of Cadence, for checking the design against the full rule deck from your manufacturing partner. These rules will normally have reference geometries, which are used to assign special constraints or values in critical regions of the design.
Some of these regions are self-explanatory. Do you have a constraint region defined under your die component to allow narrower trace and space for the die escape routing? That region will need to be passed on to the sign-off tool so that it is aware of and processes the constraint changes properly.
Other regions, however, may be more complicated. Does your sign-off tool have checks for a specific distance from the edge of the substrate, akin to plating bar trace spacing in a traditional IC package design? Is there a transition area leaving the die where things step up? The new Reference Geometry tool allows you to define these relationships between design elements and rule checks. As your design evolves, a single button push will ensure that all reference areas are fully up to date for sending out to the sign-off engine with any run.
Geometries can be generated by copying, contracting, expanding, or creating rings around areas. Perform Boolean operations between two layers, placing the output on a new layer. Build up more complicated rules by referencing previous entries’ outputs as inputs to the next action.
The advantages to consolidating these reference layers in one place are clear. Remove the worries about forgetting a critical geometry area from your sign-off pass. Reuse the operations from one design to the next through the import/export options. Most of all, have confidence that your sign-off and in-design rules are operating the same, and both give you the accurate results critical to successful design completion.
Don’t take my word for things. I believe that the Allegro platform is the best in the world for these types of designs. Download the latest software and try things out for yourself. But, remember to share your thoughts and feedback with us. That’s what allows us to continually evolve and improve the tools! Come back here often as we continue to share with you all the updates that are being made to the platform-tools.
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