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  • Tyler
    IC Packagers: Renaming Nets in a Layout
    By Tyler | 14 Jul 2020
    As the component count increases in package/interposer designs, many more of you are turning to front-end schematic tools for managing the netlist and connectivity. When working directly inside the layout design, however, there remain many cases wher...
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    Tags:
    17.4 | IC Packaging | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Automating Your LVS Text Label Generation
    By Tyler | 7 Jul 2020
    If you are using Allegro Package Designer Plus with the Silicon Layout option to design your substrates, it is likely that you are also using a formal verification platform such as Cadence Pegasus or PVS to check your physical layout against the logi...
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    Tags:
    17.4 | IC Packaging | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Accelerate Complex Degassing with 17.4
    By Tyler | 30 Jun 2020
    Degassing, other times called outgassing, is a common operation in IC package and interposer designs. As the name implies, the technology allows for gases to escape during the manufacturing process and prevent bubbling. It has a second benefit &ndash...
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    Tags:
    IC Packaging | Allegro Package Designer
  • Tyler
    IC Packagers: How to Fix Padstacks that Aren’t Showing All Their Layers
    By Tyler | 24 Jun 2020
    We talked a few months ago regarding why flip-chip padstacks are single layer pads in your design. Today, I wanted to spend just a few minutes looking at a variation on this issue that has come across my inbox more than once since that post went up. ...
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    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: Navigating Your Visible Design
    By Tyler | 16 Jun 2020
    Last week we introduced you to the new dark theme. But, we listen to your suggestions for ideas of other ways to improve your ability to move around your design efficiently. That brings me to two other items which you have your peers in our loyal com...
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    Tags:
    17.4 | Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: Welcome to the Dark Side
    By Tyler | 10 Jun 2020
    The 7th ISR (HotFix 007 or QIR1) for the 17.4 release is available for download now. This marks the first major update for the 17.4 software stream, and what an update it is! You’ll notice many new things when you download and install the new build. Let’s tal...
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    Tags:
    Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: Count Your Fingers (Without Using Your Toes)
    By Tyler | 3 Jun 2020
    Let’s talk about wire bonding today! More specifically, the unique labels assigned to every bond finger in your design and how these are import for documentation and your bonding engineer. Bond finger labels are like physical pin numbers on you...
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    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: Keep Fan-Out Routing Aligned During ECOs
    By Tyler | 26 May 2020
    When a change comes in from your IC design partner, it can be met with trepidation. How drastic is the change? What impact will it have on the package routing and (potentially) even the layer count needed to fan out the die? Will the bond finger tier...
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    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: Determining Minimum Spacing Values in a Design
    By Tyler | 19 May 2020
    I don’t remember the first time I was asked this question. At its core, the question was one of finding not the minimum constraint value in the design, but instead the minimum ACTUAL spacing value for a given set of objects in the design. As we...
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    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: The Choice Between Static and Dynamic Shapes
    By Tyler | 12 May 2020
    That title might be a touch misleading. We’re not here to talk about why to convert shapes between static and dynamic. Rather, I want to talk about why you should NOT be doing this. Every design has some conductor shapes in it (or at least a ve...
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    Tags:
    Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: Advanced In-Design Symbol Editing
    By Tyler | 6 May 2020
    We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro Package Designer layout tools allowing you to work on symbol definitions directly in the context of your layout de...
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    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: Shape Connectivity in the Allegro Data Model
    By Tyler | 28 Apr 2020
    Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad ...
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    Tags:
    Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: You Can Leave Your (Molding) Cap On…
    By Tyler | 21 Apr 2020
    Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be...
    0 Comments
    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: Time-Saving Alternatives to Show Element
    By Tyler | 14 Apr 2020
    In the Allegro back-end layout products like Allegro Package Designer Plus, it would be reasonable to assume that the most often used command is none other than “show element” (shortcut key F4). This command, runnable at nearly any t...
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    Tags:
    Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: A New Option in Bond Finger Solder Mask Openings
    By Tyler | 7 Apr 2020
    If you design wire bond packages, you’re familiar with the need for the bond fingers and rings on the package substrate layers to be exposed through the solder mask layer. If they aren’t, it becomes… rather difficult… to bon...
    0 Comments
    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: Don’t Get Stranded on Islands, Delete Them!
    By Tyler | 31 Mar 2020
    No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with no connections to them, not an idyllic private oasis in the Caribbean (sorry). Removing shape islands is something you’ve always been able to do in th...
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    Tags:
    Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: Identify Your Components
    By Tyler | 24 Mar 2020
    We’ve all seen bar codes and the more modern QR codes. They’re everywhere you go – items at the grocery store, advertisements and posters, even on websites. Did you know that, with the productivity toolbox in Allegro Package Designe...
    0 Comments
    Tags:
    Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: Design Element Label Management
    By Tyler | 18 Mar 2020
    A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...
    0 Comments
    Tags:
    Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: The Different Types of Mirrors
    By Tyler | 10 Mar 2020
    I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of m...
    0 Comments
    Tags:
    Allegro Package Designer
  • mrigashira
    IC Packagers: Five Steps to IC-Driven Package Design
    By mrigashira | 5 Mar 2020
    They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now.  The net result of this run? Well, you can't design ICs in isolation from the...
    0 Comments
    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: Variable Text Labels and Template Reuse
    By Tyler | 25 Feb 2020
    For many, the information labels always go in a consistent location in the design so that they appear at the same location on a printout of the design. If you want these text elements in the same place in all your designs, but each design has its own set of values ...
    0 Comments
    Tags:
    Allegro Package Designer | Allegro PCB Editor
  • Tyler
    IC Packagers: An Introduction to Via Arrays
    By Tyler | 18 Feb 2020
    Vias are present in every design (except maybe some lead frames and the very rare single-layer substrate). Where they are placed, and how many there are, will depend on a slew of factors, though, as we know. There are different situations and reasons...
    0 Comments
    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: RF Symbols, Coils, and Structures in IC Packages
    By Tyler | 11 Feb 2020
    So, you need to add more complicated structures into your package design. What options do you have available to you in the Cadence packaging products with the 17.4 release – whether you’re using the base Allegro Package Designer Plus or h...
    0 Comments
    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: A Boundless Bounty of Bounding Shapes
    By Tyler | 4 Feb 2020
    How’s that for a tongue twister? Go ahead, try and say it three times fast! What we’re talking about today is the “Create Bounding Shapes” tool found in the Shapes menu of both Allegro Package Designer and SiP Layout. We first...
    0 Comments
    Tags:
    Allegro Package Designer
  • Tyler
    IC Packagers: Mysteries Revealed - Why Is Flip-Chip Chip-Down the Default Library Die Orientation?
    By Tyler | 28 Jan 2020
    We’ve come to the end of my New Year’s Resolutions for 2020. Before we dive deeper into the exciting new capabilities to be found in the 17.4 release, though, I’d like to address a question I hear from new users all the time. That q...
    0 Comments
    Tags:
    Allegro Package Designer
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