IC Packaging and SiP Blogs

No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with no connections to them, not an idyllic private oasis in the Caribbean (sorry). Removing shape islands is something you’ve always been able to do in th...

We’ve all seen bar codes and the more modern QR codes. They’re everywhere you go – items at the grocery store, advertisements and posters, even on websites. Did you know that, with the productivity toolbox in Allegro Package Designe...

A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of m...

They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now.  The net result of this run? Well, you can't design ICs in isolation from the...

For many, the information labels always go in a consistent location in the design so that they appear at the same location on a printout of the design. If you want these text elements in the same place in all your designs, but each design has its own set of values ...

Vias are present in every design (except maybe some lead frames and the very rare single-layer substrate). Where they are placed, and how many there are, will depend on a slew of factors, though, as we know. There are different situations and reasons...

So, you need to add more complicated structures into your package design. What options do you have available to you in the Cadence packaging products with the 17.4 release – whether you’re using the base Allegro Package Designer Plus or h...

How’s that for a tongue twister? Go ahead, try and say it three times fast! What we’re talking about today is the “Create Bounding Shapes” tool found in the Shapes menu of both Allegro Package Designer and SiP Layout. We first...

We’ve come to the end of my New Year’s Resolutions for 2020. Before we dive deeper into the exciting new capabilities to be found in the 17.4 release, though, I’d like to address a question I hear from new users all the time. That q...

When you need to make an edit to a component, whether that is the BGA footprint in need of a pin #1 padstack change for reference of adjustments to the entire bump layout of a flip-chip to feed routability changes back to the IC design team, there ar...

For those of you who do wire-bond package substrate – whether you’re designing a single-chip leadframe, a multi-die memory stack, or a complex stack with wire-bonds, flip-chips, interposers, and spacers all in one – you need wire pr...

Designing a package substrate, there are things that many of us do that perhaps we should think twice about. One of those being using a multi-layer padstack for the pins of flip-chip dies. I understand the attractiveness of doing this, but if you’ll give me just a few moments, perhaps I can convince you to put ...

We started 2019 with the promise to cover all the topics that might interest you as we go, looking at a new area every week. To keep this promise we had a whole lot of exciting tasks. To start with we needed to know what you want to re...

A fantastic year is ending, so I want to take a quick opportunity to go over some of the lesser-known commands available to you for cleaning up and optimizing your routing for manufact...

The flow for efficiently and correctly designing a package substrate layout is a complex task. Many teams define steps to be followed by designers to make sure that rul...

Some of you are APD users, building single-chip or non-stacked multi-chip packages. Others of you are SiP Layout XL users, probably stacking dies or embedding elemen...

The most common operations in any tool are probably adding, moving, deleting… plus copying and pasting. That we all are familiar with Control-C and Control-V being shortcuts to these actions speaks to their applicability across tools we use ev...

If you’ve run the 17.4 release, you have probably seen two 3D rendering tools – 3D Viewer and 3D Canvas – present in the View menu. Why are there two? That’s a good question, and the answer lies in the type of design you ...

You should be getting used to the new 17.4 release at this point. I am willing to bet there are still exciting new improvements that you haven’t found yet. Today, allow me to show off the new materials editor.  It is likely you don’t...

While 17.4 has only been amongst you for a month, now, I’ve had a few questions regarding manipulating your layer stack-up in the new release. We covered scripting changes previously, but a quick chat about the general use model is warranted. T...

Many of you, our regular readers, are familiar with via structures. These reusable patterns of vias, clines, shape, and keep-out shapes, and return path elements allow you to escape a single pin then replicate that structure (or pattern of structures...

If you joined us last week to see the visual changes to be expected when you download 17.4, doubtless the next thing you need to know is how migrating will impact your automation. And, if you’ve installed the software already, you’re one ...

It’s here! Less than two weeks ago, on October 18, 2019, Cadence released the 17.4-2019 version of the Allegro product line. This means exciting new features, enhancements, bug fixes, and performance improvements to the tools you depend on to d...

Every package design has data sources. Die data you receive from the IC design team as they send you updated die text files and co-design die abstracts. Your downstream PCB design team may send an updated ball map spreadsheet with change requests. Obviously, your front-end schematic engineer will be pushing you updated netlist information. How do you keep track of when the last time was that you imported data from a...