IC Packaging and SiP Blogs

Most package substrates are designed as they will be placed onto the host PCB if the package were mounted on the top side. This means that the BGA’s balls are on the bottom layer of the cross-section. Your dies are mounted on the top. For wire ...

Sharp angles, whether they create a spike in a poured shape or form an acid trap between two different pieces of metal, are a problem for us all. And as designers, we will go out of our way to try and avoid creating these situations; they will still ...

If you ever have the need to remove an area of your design, you may find it to be a more complex process than you would think. Shapes in that area will, if you select them with show element, want to pick up the entire shape. That may extend well outs...

I think every traditional package designer understands what a plating bar is and the purpose it serves. There to provide electric current during the manufacturing process, each net is connected out to the perimeter of the BGA, which allows for the cu...

Having coincident edges shared across multiple layers is frequently not a desirable situation to be in. Just as we don’t appreciate degassing holes at the same position on adjacent layers – which can lead to dips or valleys in the finishe...

As the component count increases in package/interposer designs, many more of you are turning to front-end schematic tools for managing the netlist and connectivity. When working directly inside the layout design, however, there remain many cases wher...

If you are using Allegro Package Designer Plus with the Silicon Layout option to design your substrates, it is likely that you are also using a formal verification platform such as Cadence Pegasus or PVS to check your physical layout against the logi...

Degassing, other times called outgassing, is a common operation in IC package and interposer designs. As the name implies, the technology allows for gases to escape during the manufacturing process and prevent bubbling. It has a second benefit &ndash...

We talked a few months ago regarding why flip-chip padstacks are single layer pads in your design. Today, I wanted to spend just a few minutes looking at a variation on this issue that has come across my inbox more than once since that post went up. ...

Last week we introduced you to the new dark theme. But, we listen to your suggestions for ideas of other ways to improve your ability to move around your design efficiently. That brings me to two other items which you have your peers in our loyal com...

The 7th ISR (HotFix 007 or QIR1) for the 17.4 release is available for download now. This marks the first major update for the 17.4 software stream, and what an update it is! You’ll notice many new things when you download and install the new build. Let’s tal...

Let’s talk about wire bonding today! More specifically, the unique labels assigned to every bond finger in your design and how these are import for documentation and your bonding engineer. Bond finger labels are like physical pin numbers on you...

When a change comes in from your IC design partner, it can be met with trepidation. How drastic is the change? What impact will it have on the package routing and (potentially) even the layer count needed to fan out the die? Will the bond finger tier...

I don’t remember the first time I was asked this question. At its core, the question was one of finding not the minimum constraint value in the design, but instead the minimum ACTUAL spacing value for a given set of objects in the design. As we...

That title might be a touch misleading. We’re not here to talk about why to convert shapes between static and dynamic. Rather, I want to talk about why you should NOT be doing this. Every design has some conductor shapes in it (or at least a ve...

We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro Package Designer layout tools allowing you to work on symbol definitions directly in the context of your layout de...

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad ...

Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be...

In the Allegro back-end layout products like Allegro Package Designer Plus, it would be reasonable to assume that the most often used command is none other than “show element” (shortcut key F4). This command, runnable at nearly any t...

If you design wire bond packages, you’re familiar with the need for the bond fingers and rings on the package substrate layers to be exposed through the solder mask layer. If they aren’t, it becomes… rather difficult… to bon...

No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with no connections to them, not an idyllic private oasis in the Caribbean (sorry). Removing shape islands is something you’ve always been able to do in th...

We’ve all seen bar codes and the more modern QR codes. They’re everywhere you go – items at the grocery store, advertisements and posters, even on websites. Did you know that, with the productivity toolbox in Allegro Package Designe...

A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of m...

They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now.  The net result of this run? Well, you can't design ICs in isolation from the...