Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
So let’s consider a practical example of creating test benches and performing measurements, starting with how to characterize a transistor. A couple of questions to consider before starting are: What parameters do you want to measure?What types of test benches are required to measure these parameters? Let’s start by considering how to measure the ft of a transistor, ft is a standard figure of merit used by analog designers to evaluate a transistor’s performance. Later we will consider how to measure some other common transistor parameters fmax, Noise Figure, as well as, measuring device stability.First, let’s review the meaning of ft. It is defined as the unity gain frequency of a transistor’s short circuit current gain. The first point is that we need to measure the short circuit current gain so ideally the output terminal, collector [drain] of the transistor will be connected to a power supply. The next point is that we need to calculate the current gain of the transistor. For Virtuoso Analog Design Environment users, the Virtuoso Visualization and Analysis waveform calculator can be used to perform this measurement. To calculate ft, plot the current gain by dividing the collector [drain] current by the base [gate] current and then using the cross function to find the unity gain frequency. An example of calculating ft, is shown in Figure 1. Figure 1: Measuring Transistor ftWhen creating a simulation test bench the natural place to start is the actual measurement test bench. To measure ft, an RF network analyzer can be used to measure the s-parameters and then the s-parameters can be converted into h-parameters. By plotting the h21, the ft can be estimated by extrapolating the unity gain frequency of the h21. This approach works well in the lab because wideband shorts do not exist in the real world. So RF measurements need to be performed with input and output matching and a result s-parameters are the natural method for characterizing transistors. One issue when testing in the lab is the need to for separate bias and RF sources. Typically these sources are isolated with a bias T. In place of a bias T, we will use an inductor [pass the bias voltage at dc] and a capacitor [pass the RF input at frequency].Figure 2: Emulating the Network Analyzer Setup to Measure h21 Using the lab test bench introduces some complexity that is not required when performing the measurement in simulation. By taking advantage of the “ideal” nature simulation, the test bench can be simplified. In simulation, we can create a perfect short using a voltage source. The voltage source provides bias and acts as a short circuit replacing the output matching circuitry in the original test bench. The RF input has been replaced by a current source with ac magnitude of 1 so the current gain can be directly measured. The input bias is still controlled by setting a dc voltage, see Figure 3. This test bench works well when measuring ft for a single bias condition. However, it is difficult to sweep the bias current of the transistor as can be done in the lab with a bias generator.
Figure 3: Enhanced Test bench with an Output Short The next enhancement is to replace the bias voltage source and resistor with a diode connected transistor and a current source to set the bias current of the device under test [DUT], see Figure 4. Using a diode connected transistor to generate the bias voltage allows the bias current to be easily controlled. The dc bias and the RF input are still isolated by the pseudo bias T. This change to the test bench allows a designer to characterize the effect of bias current on ft so the transistor can be operated at its maximum ft.Figure 4: Improved ft Testbench Another enhancement to the test bench would be to replace the inductor and the capacitor used in the pseudo bias-T, shown in Figure 5. Virtuoso Spectre simulator provides users analysis dependent switches that can be set to open and closed depending on the analysis to be performed. This allows the designer to use the same test bench to perform multiple tests, for example, NF, fmax, etc. Figure 5: Using analysis dependent switchesThe test bench I use to measure ft is even simpler, the the bias network [diode, analysis dependent switches, and RF source] is replaced by an ideal current mirror. The current mirror provides feedback to stabilize the bias point. The current source that sets the bias current is also RF input source the bias T is eliminated. BTW, you might recognize this type of circuit, it is called a Wilson current mirror, shown in Figure 6.Figure 6: My ft Test benchTo review the test bench development process, we started by replicating the test bench we used in the lab in simulation. Then the test bench was optimized by tuning it to take advantage the “ideal” nature of a SPICE simulator. Along the way we made several improvement to the measurements process. 1) Directly measured the ft, eliminating the need to generate the s-parameters and then calculate the h-parameters.2) Added the ability to sweep the bias current so plots of ft vs. Ic can be generated, see Figure 7. Figure 7: Plot of ft vs. Ic
In closing, I hope that this example of creating a test bench and making measurements will be useful for you. Please let me know what you think.
Best Regards,Art Schaldenbrand
I am unable to understand how ft vs Ic plot is generated. How do you do a nested sweep of dc bias current and ac analysis to determine ft at each bias current?
did you ever put up a test bench for fmax?
This was indeed helpful - but to plot beta vs f, I couldnt select the currents in the transistor teminals(it was reporting that the expression did not evaluate to an object to be plotted ), So I had to put a dummy voltage source and then select the currents from its nodes. Could you explain what was the reason
1) Save the collector and base currents
2) First calculare beta.
In the calculator, divide ( collector current / base current), make sure you use the
the ac currents for the calculation:
i("/Q0/C" ?result "ac-ac") / i("/Q0/B" ?result "ac-ac")
3) Use the cross function to find the frequency when the current gain is 1
or you can convert the expression into dB20 and look for the zero crossing
cross(dB20((i("/Q0/C" ?result "ac-ac") / i("/Q0/B" ?result "ac-ac"))) 0 1 "either" nil nil)
How do you plot fT vs IC as in Fig. 7?
IFEEDBACK is a current-controlled, current source, cccs, in analogLib. The plot
shows the ac beta --> i_collector/i_base, where the lower case i is meant to show
the ac current.
If you would like the netlist for the testbench, you can find it at the following link,
What element is "IFEEDBACK" for which vref=IREFERENCE ? Is this a standard part in the analog library?
Also, how was Fig.7 plotted (what BLOCKED EXPRESSION? Was this obtained by first obtaining ft as per fig.1 and then repeating that over Ic?
This was very helpful. We are working on some printed electronics experiments and it helped me think through a way to get the Ft measurement done!