Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Recently there was an inquiry about the methodology for performing the ft (transition frequency) versus Ic measurement described in my Measuring Transistor ft blog post from July 2008:
By bid75 on September 8, 2010I am unable to understand how ft vs. Ic plot is generated. How do you do a nested sweep of dc bias current and ac analysis to determine ft at each bias current?
Initially, I was just going to fire off a quick response. However, after thinking about the question, it seemed like a topic that needed to be explored in more detail. So you are going to get this appended posting (and a really cool title). In answer to the question, the tool that performs the nested sweep is the parametric analysis in Virtuoso Analog Design Environment -- specifically, it's a feature of ADE-L. I think that parametric analysis is a useful tool and hopefully after reading this posting you will too.
1) Select the variable to sweep, ICE
2) Select the variable sweep, from X A [1µA] to Y A [10mA] with Z  steps / decadeNote: You will need to adjust the range based on the device that you are analyzing
3) To run the analysis, click on the green arrow
4) When the simulation is complete plot the results, ft and IcNote: You will need to change the X-axis variable from the swept variable ICE to collector current, Ic
Figure 1: Parametric Analysis Setup
Measuring ft is a simple application of parametric analysis. Next, let's look at some other applications. First, we will look at one common challenge designers face as power supply voltages scale down -- understanding the input common mode range of their designs. Different people have different figures of merit for the input common mode range of an operational amplifier. Here we will define the input common-mode range as the input common levels that the dc (maximum) value of the open-loop gain falls by 3dB from the peak value (see figure 2). Parametric analysis makes it easy to visualize the input common-mode range of the amplifier. Not only can we measure the values, we also get a qualitative feel for the how much margin we have before the amplifier fails.
Figure 2: Parametric Analysis Results for Input Common-Mode Range
Lastly, we will apply parametric analysis to a more complex measurement. Suppose that you would like to understand the limits of the dynamic performance of an A/D Converter-- for example, measure the Effective Resolution Bandwidth, ERBW. The Effective Resolution Bandwidth is the input frequency at which the SINAD at full scale falls by 3dB compared to the SINAD at dc. It is a useful figure of merit to measure the conversion bandwidth of an A/D Converter. Shown in figure 3 is an example of simulating the Effective Resolution Bandwidth of a five bit A/D Converter. By nesting this sweep inside of other sweeps, we can analyze the effect of circuit operating conditions on circuit performance -- for example, the effect of power supply voltage or temperature variations on the bandwidth of an A/D Converter. One comment is that you need to properly parameterize your testbench and the appropriate sweep variable when using parametric analysis. We will save the discussion of how to properly parameterize a testbench for another posting.
So the summary is that you can use parametric analysis to perform the nested sweep for analyzing ft. However, as we have discussed, there are many other applications of parametric analysis. Hope this posting was useful. As always, please let me know if you have any questions or comments!
Dear sir, I want to know how do you change X-axis variable from the swept variable ICE to collector current, Ic in ft~Ic curve?
Using the parametric tool to sweep the bias current is kind of obvious, right? The quetion I have, and it seems to me the question others have is: How do you form the nested loops? To get ft we need to do an ac analysis at each bias currrent, right? This is the inner loop. So please show how you use the cross function to get ft (was the calculator even mentioned?). So how does it work? Do you define a measurement in the calculator, and then run the dc sweep, and then when the simulation is finished do you plot the cross expression in the calculator? Believe me, we are still scratching our heads. You need to spell the procedure out more explicitly. Thanks much. We appreciate it.