Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
The nport component located in analogLib can be used in circuits for Spectre and SpectreRF simulations. It is a scattering parameter (S-parameter) based distributed multi-port element. The nport truly is a "black box"… It can be used to model dramatically different systems, such as:
It is nearly impossible to have a "one size fits all" default setting. In recent releases, a great deal of fine tuning has been done to ensure accuracy and good simulation performance based on numerous design applications. However, you still need to understand how to tailor the model for your particular application. The most common problems seen during transient, pss, hb, etc analysis with a circuit containing an nport are due to:
My favorite parameters are: dcextrap, hfextrap, passivity, and causality. These all assume that you are using linear or spline interpolation, which is recommended for most applications. Here’s the “scoop” ….
dcextrap (long delay dc extrapolation method)
dcextrap is typically used when the nport s-parameter data file models a system with long delay --and-- the DC point is not included in the s-parameter data file. One problem that occurs in these systems is the default extrapolation mechanism for the phase calculation results in an incorrect value of phase at DC, and then continues to be incorrect up to Fmin (the lowest frequency s-parameter data point). This happens when Fmin does not model the phase well enough at low frequency such that a simple extrapolation provides incorrect results.
With dcextrap=constant (default option), a constant magnitude from the lowest frequency data point is used and the dc phase is set to the real axis near the lowest frequency data point.
Using dcextrap=unwrap can improve the results by calculating a better estimate of the extrapolated phase response at DC. The DC magnitude is set based on a regression of the low frequency data. The DC phase is set by unwrapping the phase and setting it onto the real axis.
With dcextrap=hpunwrap, both the magnitude and phase are extrapolated from a regression analysis. It is similar to dcextrap=unwrap but provides an alternate approach for dc phase extraction which may be preferred for high pass characteristics.
Note that dcextrap=unwrap and hpunwrap are used only if you *do not* have a DC point in the s-parameter data file. If there is a DC data point, then this parameter is ignored.
The hfextrap parameter (long delay high frequency extrapolation method)
hfextrap=constant (default). The default behavior of Spectre's nport element is to use constant extrapolation at high frequencies.
hfextrap=linear linearly extrapolates phase at high frequencies. This can help to more closely match lab measurements when the S-parameter data is frequency limited and extrapolating the phase in a linear fashion is realistic.
hfextrap is ignored if you are using causality. When using hfextrap, you may also want to set usewindows=yes (smooth data windowing function) to help ensure model stability, particularly with s-parameter data having insufficient bandwidth.
The causality parameter corrects s-parameter data to ensure the system is causal.
When causality=no or the parameter is not set, the nport behavior is the same as in previous MMSIM releases. No causality correction is done.
Both causality=fmax and causality=auto extrapolate s-parameter data with polynomial, and apply a Hilbert transform to calculate causality violation. Then coefficients of interpolating polynomial are optimized to minimize causality error. The parameters usewindow and hfextrap are ignored when causality=fmax or auto.
When causality=fmax, Spectre corrects causality up to fmax. It either uses the default (which is 3 times the maximum frequency specified in the s-parameter data file), or it uses what the user has specified for the existing nport parameter fmax.
When causality=auto, Spectre corrects s-parameter causality up to an automatically optimized fmax (the fmax frequency is iteratively adjusted to minimize causality error) and ignores the existing nport parameter fmax. Note that the auto setting can significantly increase simulation time, therefore causality=fmax is recommended.
There are two passivity parameters: passivity and pabstol.
Due to poor measurement accuracy, the s-parameter data may be non-passive. The consequence is the time-domain simulation may not converge. The passivity parameter checks and enforces passivity of s-parameters. Possible values are no (default), check or enforce.
passivity=check ensures the eigenvalues of the real(Y) matrix are non-negative. A warning message is issued if the data is not passive.
passivity=enforce re-sets the negative eigenvalues of the real(Y) matrix to zero if the data is found to be non-passive. A notice is issued in the spectre.out.file. The pabstol parameter specifies the absolute tolerance of passivity criteria. The default is 1e-6.
Summarizing.... Good S-parameter data is the key to nport model stability and accuracy in the time domain. Most convergence problems are caused by incomplete or incorrect data.
Hi Pietro M,
I would use the analogLib nport (not the n1port). The nXports are there for legacy reasons. All enhancements/fixes/etc are in the nport.
Rational interpolation works well when you have lumped elements, as you have discovered. However, it does not work well when you have > 4 ports or are modeling a system with long propagation delay, In those cases, rational is not as robust nor as accurate as the linear/spline algorithms.
Good morning, I wanted to use the N1PORT component for the transient simulation of a measured device, but I had problems. I hence tried to create a capacitor with N1PORT and S=(1-jwRC)/(1+jwRC), with f from 0 to 1GHz with 500KHz step. The simulation works well in "Rational", but with "Spline" and "Linear" interpolation there is a static current equivalent to a 12.5KOhm parallel resistor, which produces 80uA current on 1V DC voltage. I tried with all the options I had in the schematic entry without improving the simulation.
Hi Stephan, you are absolutely correct. Rational interpolation is a reasonable choice if you have lumped elements. The rational model is not as robust and accurate as the convolution based model (linear or spline), particularly when the s-parameter data models distributed systems with long propagation delay, or the DUT is a multi-port system with the number of ports > 4.
Hi, although not everybody like it: If you know your s-parameter are presented well with a lumped element circuit (like package or LC filter, etc.), then 'rational' is a good choice!! Use not a too large 'order', usually it is best to use one more than the expected order. With rational you often get best transient behavior and extrapolation. Try to learn for your own: Make a little LC filter, simulated + save s2p file, then change testbench to include the s2p via nport and run e.g. a pulse step - and play with port settings. This way you can prepare for more complex cases.