Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
From time to time, SpectreRF users simulate very large, extracted-view circuits in 2+ tone QPSS. In many of those cases, memory requirements exceed the available resources. When that happens and small-signal approximations aren’t applicable, the user is typically stuck.
The solution below and attached database describe a technique that achieves an order-of-magnitude reduction in memory requirements by converting an N-tone QPSS problem to an equivalent (N-1)-tone envelope-following analysis.
This is a 2-tone signal in the common HB representation:
We can also look at this as a modulated carrier, with the modulation function:
We run an envelope analysis to compute the modulations at each node and harmonic and calculate the multi-tone representation using DFT.
* Numerically, envelope simulation is similar to HB simulation repeated at each time step.
* By looking at a 2-tone signal as a modulated carrier, we convert a 2-tone problem to many smaller 1-tone problems.
* In general, we can convert an N-tone HB analysis to a series of N-1 tone analyses.
Basic Approach in Virtuoso:
* Use a Verilog-A module and transient simulation to generate I/Q components of the 2-tone modulation function
* Apply the I/Q components using the PORT element’s Modulation parameters and run an envelope simulation
* Run envelope analysis over N periods (the period is just the inverse of a half of the frequency spacing); this lets all transients expire (we are looking to reach the envelope steady-state)
* Use adaptive step envelope for best simulation accuracy, but use equally spaced strobe output for best postprocessing accuracy using DFT.
* This currently works with 2-tone simulation.
* This should also work with 3+ tones, but currently does not. CCR 979403 has been filed for this issue. Once fixed, you will be able to apply this to 3+ tones.
In this example, you wil see:
* Creating the IQ signal
* Running envelope simulation
* Results comparison
Creating the IQ signal
Use the attached database testcase.tar.gz. This is available on Cadence Online Support in Solution 11774216.
Open library test_2t_env.
Simulate the cell generate_envelope from state spectre_state1.
Generating the 2-tone Envelope
The ADE setup lets you specify tone spacing, power in each tone, the number of samples per period (N) and the number of periods (cycles) to store.
You get something like this:
This now represents the envelope of our two-tone signal, and we’ll run and envelope analysis with it as the source next.
Verifying the Source Signal
First, we’ll run a very simple example, just to make sure that we get what we expect.
Open the test_port schematic view and observe the port’s relevant settings.
Port Edit Properties form:
Running the Simulation:
Open test_port->spectre_state1 and simulate.
Plot the ‘right’ and ‘left’ outputs: (Note that 'right' and 'left' are defined below).
What are 'right' and 'left'??
* ‘Right’/’Left’ is what you would see to the right/left of the carrier when you look at the spectrum analyzer.
* This is just an artifact of how we post-process the envelope (to be explained later).
* Since the ViVA DFT works on purely real waveforms, ‘left’ is really the image of the negative frequency spectrum.
* So, we have a -20 dBm tone, offset 1 MHz from the carrier, and another of equal power, offset -1 MHz from the carrier. This is exactly what you’d expect.
Running a 2-tone HB Simulation for Reference
Open test_hb_2tone, which is just a behavioral LNA simulation.
Run test_hb_2tone, which is the excitation we saw in the above paragraphs, applied in an HB simulation.
Running an Envelope Simulation on the LNA
This is the same as the previous example, except that uses envelope simulation with the PORT element as set up earlier.
Since the LNA has no memory and the excitation is symmetric, ‘left’ and ‘right’ are the same.
HB and envelope give nearly identical results!
Post Processing Background
* To calculate the spectrum, we would ideally take the complex DFT of the waveform and convert to dBm. The formula goes like:
* Since there is no complex DFT in ViVA, we do something like:
Right Spectrum = dbm(DFT(real(X(t)/2)+j*DFT(imag(X(t)/2))
Left Spectrum = dbm(conj(DFT(real(X(t)/2)))-j*conj(DFT(imag(X(t)/2))))
* Note that, in all cases, we want to process only the last cycle of the waveform (when the steady-state is reached).
* The expressions are a bit messy. They are shown only for reference below. Use the ADE state as a bench rather than attempting to enter the expression from scratch.
Spectrum Post Processing Expressions 'Right'
(10 * log10((pow(abs(((dft(real(harmonic(v("/out" ?result "envlp_fd") '1)) ((pv("/cycles" "value" ?result "variables") - 1) / pv("/deltaf2" "value" ?result "variables")) (pv("/cycles" "value" ?result "variables") / pv("/deltaf2" "value" ?result "variables")) pv("/N" "value" ?result "variables") "Rectangular" 1 "default") + (sqrt(-1) * dft(imag(harmonic(v("/out" ?result "envlp_fd") '1)) ((pv("/cycles" "value" ?result "variables") - 1) / pv("/deltaf2" "value" ?result "variables")) (pv("/cycles" "value" ?result "variables") / pv("/deltaf2" "value" ?result "variables")) pv("/N" "value" ?result "variables") "Rectangular" 1 "default"))) / 2)) 2) * 10)))
Spectrum Post Processing Expressions 'Left'
(10 * log10((pow(abs(((dft(real(harmonic(v("/out" ?result "envlp_fd") '1)) ((pv("/cycles" "value" ?result "variables") - 1) / pv("/deltaf2" "value" ?result "variables")) (pv("/cycles" "value" ?result "variables") / pv("/deltaf2" "value" ?result "variables")) pv("/N" "value" ?result "variables") "Rectangular" 1 "default") - (sqrt(-1) * dft(imag(harmonic(v("/out" ?result "envlp_fd") '1)) ((pv("/cycles" "value" ?result "variables") - 1) / pv("/deltaf2" "value" ?result "variables")) (pv("/cycles" "value" ?result "variables") / pv("/deltaf2" "value" ?result "variables")) pv("/N" "value" ?result "variables") "Rectangular" 1 "default"))) / 2)) 2) * 10)))
Have fun simulating!
Hi Frank, I agree that rapid IP2 and IP3 are suitable for small signal situations. The original post is specifically for those situations where Rapid IP2/IP3 are not appropriate (small signal approximations are not valid). best regards, Tawna
An alternative possibility for weakly nonlinear circuits are the Rapid IP2 and Rapid IP3 analyses, which are special analysis options to the AC analysis (for amplifiers) and to the PAC analysis (for mixers). The algorithms behind these methods are described in US Patent 7774176.