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More of our customers are using Incisive for transaction level modeling (TLM) and functional virtual prototyping, analyzing design characteristics before committing to RTL architectures. SystemC is the design language of choice for most of these users, because it is an industry standard, and Incisive provides important connections into the RTL verification flow. Similarly important is the employment of an advanced testbench language and methodology that allows for easy reuse of verification IP from TLM into more exhaustive RTL functional verification.
Today Cadence announced an important advancement in technology and methodology for extending OVM to include SystemC or e languages. By extending OVM to include SystemC, verification IP created early in the development of the system can be more reused in RTL functional verification that is the focus of SystemVerilog and e language testbenches. This advancement has long been a goal for those performing early system level testing, and can now be realized more easily.
You'll find lots of useful information at www.cadence.com as well as www.ovmworld.org!