Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Seems logical, but unfortunately, I run into customers today that grumble about their past experiences such as:
"Gosh, I wish our chip wasn't so big. How did that happen?", says one ...
"Our memory requirements grew and grew, out of control, almost couldn't fit it", says another ...
"If I knew where we'd be today (which is not where I want to be), I wouldn't have bought that IP to begin with, it just doesn't make sense!", a manager says...
and just as bad ...
"I would have never approved this chip project if I knew this (this = exceeding our constraints) was going to happen! What a waste of money, now we're in trouble ... ", one very unhappy camper.
In the past, many of the above thoughts also often entered my teams' minds as we designed numerous chips. After initial planning, coding, implementation, we would just hack away at it, and at times, eventually be forced to make sacrifices in our design (hardware and/or software = our 'system') in order to minimize the effects of an earlier decision(s) but still meet the market needs. So, how did this all start? ...
Usually, it begins with a RFQ, hopefully the most orderly formal documentation that you hand your vendors (or, if you're in a COT flow, you may have something similar but for internal processes). For background, RFQ = Request for Quote, meaning you want to see how much you're going to pay for your chip development (and your return on investment) given your set of input needs. (for example, you *think* your design will be 5 million gates, have ~5M bits of memory, 500 I/Os, you'll need a USB PHY and controller, etc ...) It's basically a rough specification of your design, enough information to build your chip. From the RFQ, you'll eventually usually get a bid (or bids if multiple vendors, or a quote, if internal source), then you haggle on the price until you settle on it. In the mean time, in parallel, depending on your design, there could be a ton of information in email, spreadsheets, documents that's all over the place that needs to be processed and summarized to feedback into the RFQ bid. From past experience, this can be a big pain, since data can change very fast, thus requiring recalculation. Even worse, the data is all over the place, in numerous people's hands depending on who owns what relationship. No consolidated central location of information to collaborate on. This is where the process can break down. Eventually, if things spin out of control, you're left with having to decide on a approving a project based on information that you believe is accurate. In any case, you sign up for the project, then, eventually, get bitten due to some inaccuracy in the earlier assumptions when the decision to approve the project was made.
This is where a collaborative system can help - help give solid input when it's needed - before you commit and spend the dollars on the resources including IPs. What is needed is a 'place' that consolidates all the information into one central location that everyone understands - a database and language that everyone understands easily. With this database, all key decision-makers should be able to use it easily. Ideally, this would be the best solution, and fortunately, Cadence acquired a company called ChipEstimate(.com) in 2008 which provides this solution today.
If interested, you can check out two of their products: InCyte and Chip Planning Solution.
In a nutshell, these software tools have helped many teams collaborate on early chip estimations as well as post-implementation analysis when more information is available. Cadence's ChipEstimate solutions provide a holistic view of the chip estimation process,
leveraging a powerful IP database, helps drive better RFQ analysis and ROI, and will give soon-to-be released low power estimation capabilities (which we'll explore in upcoming blogs). The benefits are good enough that vendors that you may be working with may be using ChipEstimate's tools for their RFQ responses.
So ... make those right decisions with the right tools, before you start your project!