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Can you think of a more critical application for system-level verification than making ABSOLUTELY CERTAIN a missile carrying nearly 5 Megatons of nuclear payload doesn't have any "bugs"? We've all seen enough James Bond and Superman movies to understand what can happen with "wayward" missiles!
So I wanted to point out a very good article appearing in this month's issue of Evaluation Engineering. It describes how a team of engineers at Draper Labs used a verification flow from Matlab Simulink --> Virtutech Simics --> Cadence Palladium, to test/validate the new (and very complex: four flight-computers with multiple sensor subsystems) inertial guidance system for the Trident missile. You will appreciate the utter and total lack of marketing hyperbole ("written by engineers, for engineers" is their motto! :-)
Cadence has a tight partnership with Virtutech to enable exactly what the Draper Labs engineers did (among other things).
In principle, the Draper team followed the same system-level verification approach Cadence has implemented under the label of "TLM-driven Verification using OVM" for SoCs: Starting at a high level of abstraction (such as Matlab, C/C++), at each development stage, engineers use progressively higher fidelity/more exact models of their system components to validate their design with greater confidence and accuracy. The goal is to do as much verification as possible at higher levels of abstraction, where simulation is faster, and bugs usually more obvious. "Detailed verification" is then performed at the lower levels of abstraction on those areas that couldn't be thoroughly verified at the higher level. The "secret" is understanding how to manage the reuse of testcases/testbenches throughout the process in a manner that minimizes duplication/repetition of verification effort, yet covers the entire space the needs to be verified.
Many engineers in commercial industry have been dismissive in the past of their colleagues in the Mil-Aero domain. What many of them don't realize is that the SoC development challenges causing so much angst at semiconductor companies today, System Engineers in Mil-Aero have been tackling for 50+ years! Compared to Mil-Aero, most "best commercial practices" today appear "seat-of-the-pants". But with commercial SoC development NRE costs approaching Mil-Aero levels (at $100M+), the days of "seat-of-the-pants-semiconductor-engineering" are probably over.
Maybe it's time for commercial IC designers to borrow a few pages from their Mil-Aero colleagues' playbook?