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An open IP platform for you to customize your app-driven SoC design.
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This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
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CDNLive! EMEA will be held in Munich again this year, and
there’s lots of news about Cadence’ offerings to address the productivity gap
in Systems Realization. Here are the System Realization activities, customer
presentations, and Cadence presentations you may choose to attend:
Tuesday, May 4
13:30 - System Design & Verification Techtorial
• Part 1: TLM-driven design and verification; model
refinement for high-level synthesis
• Part 2: System Level Low Power Design
Wednesday, May 5
8:40 - 9:20Cadence KeynoteJohn Bruggeman, Cadence Chief Marketing Officer The Way Forward: A Blueprint for Transformation
10:30 SDV01Efficient scheduling of emulation workloads using LSFArm Holdings
10:30 AC01Lead institution for Advanced SoC Verification
Techniques: HyperTransport 3 – An ExampleUniversity of Heidelberg
11:00 SDV02Bandwidth and throughput measure for systems and
interconnects with Cadence Incisive® Verification IPs (VIPS)STMicroelectronics
11:30 AC02Simulate a microcontroller debug environment utilizing
SystemVerilog DPIHochschule Regensburg
12:00 SDV04Early integration of embedded software into the metric
driven verification processCadence Design Systems
13:45 SDV05Fast SoC Architecture Exploration Using Traffic
Simulation TechniquesArm Holdings
14:15 SDV06Integration of C++ software with ISX for embedded software
verificationCadence Design Systems
15:15 Demo 1: SW development and Virtual Prototyping using IES, ISX and
Fast Models from ARM
16:15 Demo 2: TLM-driven IP/subsystem design with HLS using
17:15 Demo 3: Customer Case study: ensuring high-quality and easy
integration of IPs using Palladium 18:15 Unveiling of the Palladium XP verification
computing platform, Accelerating Time and Improving Quality of System
Thursday, May 6 8:45 SDV07Co-Verification of an interrupt-based firmware for a
complex control sub-systemEASii IC
9:15 SDV08Managing Complex SoC Validation using emulation in
conjunction with fault insertionSTMicroelectronics
9:45 SDV09Cadence System Design & Verification RoadmapCadence Design Systems
11:15 SDV11ESL, The Road to Glory, And Patches on The Way - Real
Stories about Using ESL Design Methodology in Product DevelopmentGlobal Unichip Corp
11:45 SDV12Developing synthesizable IP modules from TLM 2.0
descriptions – A methodology case studyCadence Design Systems
12:15 SVD13Extending the value of traditional in-circuit emulators
to software virtualization using fast SCE-MI transactions to ARM processors Arm Holdings
12:45 SDV14High Level Synthesis of the CHStone Benchmark Suite using
Cadence® C-to-Silicon-CompilerUniversity of Tuebingen