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In the continuing effort to make high-level synthesis more viable to mainstream RTL designers, Cadence has released version 10.1 of the Cadence C-to-Silicon Compiler (CtoS).
This new release continues the recent trend towards overall ease-of-use and Quality of Results. The already popular CtoS GUI has been expanded to now allow quick exploration of all loops, function calls and arrays within the design. The expanded Control and Data Flow Graph viewer easily visualizes the control structure and flow of data through the design – all while being cross-linked to the Source viewer and all other windows in the CtoS GUI. The new Relaxed-latency mode lets CtoS automatically choose where to add states to the design, thus accelerating the process to lead designers to optimal results.
Integration is the other main theme in CtoS 10.1, which has tight links to Cadence Incisive verification, where simulations of the input SystemC, generated RTL, or fast behavioral models can be kicked off right from within the CtoS GUI. Incisive can now also read the CtoS database, and thus has all the links between the SystemC and the generated Verilog, so users can keep their focus on debugging the higher abstraction SystemC while actually running lower abstraction Verilog under the hood.
CtoS continues to have tight integration with the Encounter implementation flow to achieve predictable timing closure in logic synthesis, easy equivalency checks with Conformal LEC and a true top-down, patented ECO flow where a small change in the input SystemC results in a predictably small change in the generated RTL. CtoS also offers a compact patched netlist due to integration with Conformal ECO.
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