Get email delivery of the Cadence blog featured here
For a while now, Cadence has been providing leading
verification solutions and methodologies such as metric driven
verification (MDV). MDV guides verification projects from initial planning
to verification closure. Engineers need automated verification management
solutions that utilize metrics. Cadence metric-driven technologies automate
time-consuming manual verification tasks at the block, chip, system, and
project levels. Using a metric-driven approach, system designers and
verification teams can streamline the verification process and better analyze
failures and coverage to debug their designs.
This year, to meet the system level requirements of the
System Realization component of the EDA360
industry vision, Cadence has augmented its metric-driven verification
methodology to collect metrics from accelerated hardware and to analyze design
failures more quickly. But this capability works with no ordinary hardware
You see, in order to efficiently collect metrics and analyze
failures from a hybrid verification environment consisting of both software
simulation and hardware acceleration, the use model must allow a seamless
transition from software to hardware - and back. The engineer should be able to
easily choose whether to run simulation on a workstation motherboard or in an
accelerated hardware - and maintain control while reaping the benefits of a
familiar software debug environment. In Cadence's verification computing
platform, called Palladium
XP, we refer to this capability as "hotswap."
If you're planning on attending Design Automation Conference
(DAC) 2010 in Anaheim
next week, be sure to stop by the Cadence booth to learn more about MDV for
acceleration and hotswap. Cadence will be demonstrating "Metric Driven Verification for acceleration with Palladium XP."
You'll see how metrics can be collected from hardware and how users can easily "hotswap"
back and forth between software simulation and hardware acceleration. You'll
see how this capability can help you reach design closure more quickly.
Realization demos at DAC 2010
Live: HW/SW co-debug with ARM based design demo
ARM VSTREAM demo
Wind River Simics demo
Look for these at the System
Realization pod at the Cadence booth, Hall B #1334.
XP Verification Computing Platform
2010 tutorial: OVM Advanced Application tutorial with OVM Acceleration
XP video demo - Preview