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The EDA360 industry vision document shows how growing complexity and application-driven development are requiring orders-of-magnitude improvements in design productivity. With its new Reference Flow 11, TSMC has taken an important step towards a standard approach that will help customers develop software earlier and produce silicon in less time with fewer resources. TSMC has extended their Open Innovation Platform (OIP) to include new reference flow categories of system level design that at first glance appear far removed from the interests of a foundry. However, by reducing the costs and schedules for creating systems and silicon designs, TSMC will directly impact the number of viable designs that have a chance to scale to high volumes by hitting their market window earlier.
Cadence has contributed our latest innovations in system level design, synthesis, and functional verification to the TSMC reference flow to enable the success of our mutual customers. The Cadence contribution is unique in that it is not only a flow with examples, but also provides a complete modeling and verification cookbook, including a modeling architecture and design refinement methodology needed to successfully design at higher levels of abstraction. The key requirement is not only to create designs, but to also enable early software development, meet the requirements of silicon constraints (area, timing, power), enable speedier functional verification, and increase the reusability of the design IP.
The methodology prescribes how best to model for high level synthesis and be successful by applying the Cadence C-to-Silicon Compiler to produce RTL. By addressing the unified requirements of virtual prototyping and high level synthesis, the benefits of higher level verification can be leveraged (Figure 1). At the same time, functional verification must still be implemented fully at the RTL level.
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This figure shows starting the design at a high level (pure functional), refining it step by step down to RTL, and reusing both design and verification through all refinement steps.
Synthesizing a high level model to RTL that meets area/timing/power (with good Quality of Results or QoR) requires powerful algorithmic technology, as well as an intuitive use model and GUI to enable efficient designer analysis and intent intervention. It is also important to be able to retarget the source IP to other applications by providing different constraints. An ECO capability that makes late changes very efficient to implement is crucial for full adoption of this solution.
Probably the most valuable capability of high level synthesis is to
always use the high level model as the golden source and make all
changes to that model. This requires that functional verification be completed on the high level model. The verification flow in Figure 1 is inefficient unless the goals are carefully captured and tracked. Figure 3 shows three main abstraction levels, and how the design and verification environments are reused from one stage to the next. Planning what should be verified at each stage is critical for harvesting value from this reuse, and Cadence provides a comprehensive verifciation planning solution for addressing multiple levels of abstraction. By capturing the verification goals for each stage in a verification plan, users can employ automated tools to measure verification completion for each stage.
We really enjoyed working with Tan Li Chou and Ashok Mehta of TSMC on this project. Customers can access this methodology from either TSMC or Cadence. TSMC makes their reference methodology available to their customers. Cadence provides the TLM design and verification methodology to our customers. Please contact your sales representative to get the latest information.