Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
If you have not yet seen it, Jim Hogan and Paul McLellan wrote
a great piece over at EE Times entitled "The evolution of design methodology"
Their conclusion is that the chip design industry is in the
midst of another major shift to one where chip design becomes software-centric.
In other words, system houses define the end-product, and much of the
differentiation now comes from software. This software lives on across multiple
generations of SoC's. So they are building SoC's so that they run their
software most optimally for the desired system spec (cost, performance, power
consumption, etc). The prototypical example is the A4 chip that Apple designed
to power the iPad. The money quote is "the application drives the hardware."
The article also mentions that in order to design algorithms
that run the software load optimally, "a lot of the algorithms that will be
implemented in silicon (as opposed to running on a microprocessor or digital
signal processor) are written in C or C++ and not RTL."
Given the size and complexity of designing and verifying
these SoC's, there is necessarily a lot of re-use of blocks and subsystems. This
also lends itself to designing in C or C++ and not RTL, since RTL captures the
micro-architecture details associated with the target hardware. As a designer,
you would structure your RTL differently depending on whether performance, power,
or area was the primary concern, and even the target process technology would
influence the RTL.
Jim and Paul have always had a way of distilling complex concepts
into message that are clear to me, and this is no exception. In order to enable
software-centric hardware design, we are going to have to evolve hardware
design from RTL to SystemC. To make that work in the real world, we will need
High-Level Synthesis (HLS) tools that enable entire blocks and subsystems to be
specified in SystemC and synthesized to
RTL that can be implemented through production RTL-GDSII systems and achieve power,
performance, and area that is comparable to hand-crafted RTL.
Over the past few months, I too have been
evolving (my wife says "finally") -- from
RTL synthesis to HLS. I have been working with the C-to-Silicon Compiler team,
and I'm seeing customers achieve the promise of production-worthy HLS (see references below). Now we
need to help support the industry make this large-scale shift. So stay tuned to
and Renesas Enhance Productivity with New System-Level Design Approach
Sets New Productivity Benchmarks with TLM-Drive Design and Verification
A user's first look at
of Cadence C-to-Silicon Compiler Accelerates in Japan