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Monday is tutorial day at DAC, and this year the highest-attended tutorial was Synthesizing SystemC to Layout, led by Michael Bohm of Intel. The first session had over 100 attendees, standing room only:
Later sessions each had over 50 attendees.
The tutorial featured topics ranging from designing using SystemC to high-level synthesis to verification, and Mike discussed some of the productivity benefits that he has seen, especially in terms of verification throughput. The main takeaway was that high-level synthesis is here, it works, and you should be using it in production now.
But the biggest takeaway was the amount of engineers who attended this tutorial. It seems that this really is the time when we begin to see widespread adoption of SystemC design and verification along with high-level synthesis.
It has taken the industry a while, but now we are seeing timing/area/power QoR that meets or beats that of hand-crafted RTL. One of the keys is having embedded production RTL synthesis that can be used to constantly measure QoR as the HLS tool performs its optimization. And HLS offers the ability to quickly explore a broad micro-architecture solution space, so we see a lot of customers get significantly better QoR because they find a better micro-architecture.
Could someone highlight the performance of System C design high level synthesis when subjected to high level synthesis in terms of gate size produced and timings.. How close it will be w.r.t the traditional RTL based flow.