Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level synthesis. Given that it is a new way of doing design, we have been holding user local groups to get customers together with Cadence people to share experiences, information, and ideas so that we can all benefit.
We have held these user groups so far this year in Israel, Japan, and internally to a large customer. To give an idea as to what is typically covered, we can look to Japan which hosted the most recent one.
The morning session was open only to active customers of C-to-Silicon. There were about 25 of them, and they were treated to a tips and tricks session led by one of Cadence's leading applications engineers. This was followed by a roadmap session from a Cadence solutions architect, outlining our plans for further development of generic point-to-point communications interfaces.
The afternoon session was open to both existing and prospective customers, and over 30 new attendees joined, bringing the total to over 55. The highlight of this session was a presentation by Maesato-san of Ikegami. Those outside of Japan may not be familiar with Ikegami, but they make television cameras, studio monitors, and other broadcast equipment. The chip covered in this presentation was for a studio television camera and targeted to a Xilinx Virtex-6 FPGA. It was designed by 7 engineers, 6 of whom were novices to high-level synthesis.
They chose high-level synthesis and C-to-Silicon not only to improve design and verification productivity, but also because they wanted the design to be more easily re-used. They ended up designing 97% of the 8.7M gates with SystemC and C-to-Silicon; the rest were IP blocks. They were able to achieve 150 MHz on the Xilinx device, and when experimenting with retargeting for a 90nm ASIC, they managed raise the frequency to 300Mhz and reduce the power to 1/7th of the original. From a verification standpoint, Maesato-san said that they were able to detect 95% of the defects at the algorithm verification stage before RTL simulation.
Overall, Ikegami achieved their targets for frequency, throughput, and area. And most importantly they were able to very easily re-target the design from the intended FPGA to their experiments with the ASIC. Maesato-san requested some improvements to C-to-Silicon, but gave it a passing grade overall.
With high-level synthesis still such a new technology and methodology to most designers, sessions like these where new and existing customers can share experiences are extremely valuable. We will continue to hold these regionally where and when it makes sense, and if you would like to participate please contact your local Cadence representatives or you can contact me directly.