Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Earlier this year, Cadence announced the expansion of its VIP
Catalog to include Accelerated VIP (AVIP). AVIP is used together
with Cadence's Verification Computing Platform to enable RTL verification. AVIP running on the Palladium XP platform
consistently executes hundreds of times
faster than with simulation. Obviously this is great news for validation
teams since designs routinely exceed 50Mgates these days and much greater
performance is needed.
AVIP is also proving to be uniquely suited for
another purpose: driver/firmware
integration and validation. Cadence is seeing strong demand from our
customers for this need.
One example I've been closely monitoring is Samsung Memory. I thought I'd draw your attention to it since
many of our customers could similarly benefit from this approach.
Samsung has been using Cadence AVIP to verify their new PCI
Express based solid-state drive (SSD) design.
Samsung SSDs are typically being employed in laptops and servers to
reduce power and space and increase reliability relative to traditional hard
A bit of
This year Samsung Memory added a PCI Express interface to their
SSD controller design. The PCI Express
design addition significantly increases transaction rates and reduce latencies
relative to earlier SSSD generations. To
verify the block level protocol compliance of the new interface they began by
using Cadence's simulation VIP. This proved
to be highly effective. However, when the
time came to do firmware/driver validation at the SoC level, they found the simulation
environment wasn't sufficiently fast. In
fact, Samsung determined they'd need a validation environment capable of delivering
hundreds of times greater performance.
When they turned to Cadence for suggestions we recommended using our PCI
Express Accelerated VIP (AVIP) with a C++ user interface designed for Palladium
XP simulation-acceleration. Since Samsung
had already used our PCI Express simulation VIP, the transition to AVIP was even
more straightforward than usual. Within
three weeks the accelerated environment was up and running. This in itself was highly advantageous since it
meant Samsung's driver developer/integrators would become productive much
sooner than if they'd had to wait for an FPGA prototype. It also enabled Samsung to realize validation
productivity gains of 100%. See the Samsung
Memory success story for additional details.
Samsung's experience, taken together with other customers has made
clear that driver/firmware validation is becoming crucial step in SoC level validation. In fact we are seeing rapidly increasing
demand for this use model.
Cadence AVIP optimizes Acceleration/Emulation to enable software
driven use models. Seeing this trend we are
already working on ways to make firmware/driver validation even easier and
faster. If you've got a project nearing
the SoC validation phase I'd urge you to connect with Cadence. We're confident that AVIP in conjunction with
our Palladium XP Verification Computing Platform and RTL simulation can help
you to improve productivity and quality in your projects.
/* Style Definitions */
mso-padding-alt:0in 5.4pt 0in 5.4pt;
mso-fareast-font-family:"Times New Roman";