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This year's Design Automation Conference is less than a week away, and it's time for my preview of what to see at DAC. Last year I had likened my passion for system-level design to the Energizer Bunny, keeping on drumming. Maybe that year was the DAC of system-level design. The trend continues. We have even more customers and partners presenting at the Cadence DAC Theatre on system-level design and verification, but as I wrote last week in my Blog in Chip Design Magazine, from here on out we are really looking at a new time in the front end of EDA. Alberto Sangiovanni-Vincentelli had predicted the key role of software in his keynote at the 40th DAC ten years ago, likening the age we are in again to the "Age of Gods" as described by Giovan Battista Vico. Former Montavista founder and Linux guru Jim Ready recently started calling it "Software Driven EDA".
All the system-level design drivers I had outlined last year - technology consolidation continuing, design chain enablement becoming a key requirement, standards enabling interoperability, links to verification finding adoption and foundries embracing system-level - are still key elements driving the direction of EDA. Software sticks out though as main requirement, both enabling software development at all layers of the software stack as well as using software itself for verification.
Besides enabling software -- literally all partners and customers in the list of my recommended DAC activities talk about software -- the main trend that becomes clear when looking at the customers and partners presenting. It is the connection of the different verification engines - virtual prototyping, RTL simulation, acceleration & emulation and FPGA based prototyping.
As previously outlined, none of the engines fits all needs users have. Each one of them has specific sweet spots in the design flow, combined with supporting use models.
Virtual Prototyping is primarily used for early software development and verification of driver software as well as bring up of operating systems and middleware. Its other supporting use models are:
RTL Simulation is used primarily for hardware verification of IP blocks. It allows advanced verification using specialized test benches including SystemVerilog, Specman e, etc. Other supporting use models are:
Emulation is used primarily for "In Circuit Emulation," verifying hardware - sub-systems and systems on chip - in its system environment, which includes connections to peripherals using rate adaptors, as well as the software running on processors in the system. This is by far the biggest portion of the HW assisted verification market. Other supporting use models are:
FPGA based prototyping is primarily used for software development of lower level portions of the software stack and OS bring up, as well as hardware aware optimization of middleware, all in the context of real world peripherals. Other supporting use models are:
So this Design Automation Conference clearly is showing off Software Driven EDA, and it may well be the kickoff of hybrid engine combinations as well. See you next week!