Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
2013 was a banner year for high-level synthesis and C-to-Silicon Compiler in particular. We saw our customers take on over 75 new projects using C-to-Silicon, much of that coming from expanded adoption within our existing customers. These designs spanned everything from algorithm-intensive designs like image processors to control-dominated designs like H.265 and high-speed cache controllers to various mixtures such as automotive and networking applications.
As part of this expansion effort, the focus of our new feature development has been on delivering what these new groups need to more easily adopt C-to-Silicon. In almost all cases, the designers were new to high-level synthesis (HLS), coming from a register-transfer level (RTL-) centric background. In many cases, the requirements involve more easily adapting C/C++ code from their algorithm teams. In any case, we spent a lot of time working directly with and listening to customers so we could make HLS easier to adopt for new hardware design projects.
These capabilities were delivered over the course of 2013 - if you upgrade to the latest version on downloads.cadence.com you will be able to take advantage of these new capabilities and more. All new features in each release are detailed in the "Release Notes" in the first chapter of the C-to-Silicon Compiler User Guide. But here is a quick overview I put together with the help of Felice Balarin, who in his role as a Sr. Architect in Product Engineering spends a lot of time working with customers and then specifying what we need in each release.
Ability to pipeline functions. Older versions of C-to-Silicon required combinational C functions that needed more than one clock cycle to complete to be inlined in order to be pipelined. This allows you to take significantly more complex designs into C-to-Silicon without re-writing the source code and decomposing them into smaller pieces. This makes it much easier to get the best quality of results for new designs. This command is in the popup menu for Functions in the GUI, or with the "pipeline function" text command.
Memories with a read latency of three. Previously the max read latency supported for memories was two for built-in RAMs, prototype memories, and vendor RAMs. Now if your design requires a read latency of three, the "-read latency" option for "allocate_memory", "allocate_prototype_memory", and "allocate_builtin_ram" supports values between one and three. This increases the class of design for which C-to-Silicon can be used.
RTL schematic viewer. We have always taken care to try to generate RTL that is as readable as possible for machine-generated code. But it's much easier to grasp the structure and flow when it's presented visually, so we have included a cross-linked RTL schematic viewer in the GUI, complete with searching and filtering. Additionally, the timing-critical paths can be isolated as schematics.
Critical path viewer and corresponding RTL schematic:
Pragma "ctos keep_signal" for white-box verification. "White box" verification requires that the testbench have read access to signals internal to a module (the opposite of "black box", which would only allow for reading the inputs and outputs). Sometimes those signals are optimized away or transformed during high-level synthesis. We have added a pragma that specifies that an sc_signal be maintained post-synthesis for verification purposes.
Support for separate memory clocks. The aforementioned memory allocation commands now have a "-clock" option in order to specify a separate clock signal for accessing the memory. The clock still needs to be at the same frequency as the module's main clock, but by having a separate clock signal you can now control the clock to the memory and memory interface logic in order to save switching power.
Sequential functions with memory accesses no longer need to be inlined. This is pretty self-explanatory, and it was developed to enable more architectural exploration freedom, and the ability to handle more complex designs that would otherwise have to be decomposed
Packed structs. When converting composite data types into bit vectors, C-to-Silicon always aligned components to byte boundaries. This approach is usually beneficial because it simplifies accessing logic, but sometimes it generates redundant logic. But now by using a pragma, you have a choice of object models in order to tune your quality of results.
C-to-Silicon directives embedded in source code. The C-to-Silicon use model always mandated that commands be issued via the GUI or in Tcl. This was to separate the functionality from the implementation, one of the key benefits of high-level synthesis. However, there are certain cases where designers require control over the particular implementation of a chunk of code. A good example is using "#pragma ctos create_protocol_region" to specify that the C-to-Silicon Compiler scheduler not add or remove states in the communication protocol section of code.
Additionally, there were many minor usability enhancements added, including: