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For me, this week was almost entirely consumed with the Design and Verification Conference and Exhibition (DVCon) at the familiar DoubleTree in San Jose. The hotel has replaced its chandeliers with shiny new space-age fixtures, but otherwise, I felt at home with the usual strong technical program and many chances to network with customers and colleagues. Following up on my preview post a few weeks ago, I will provide some observations on the sessions and other events that I was able to attend.
As has been the case at other recent verification-related events, portable stimulus emerged as one of the hot topics. My time at DVCon was book-ended by two tutorials that I helped organize, both with significant content related to portable stimulus. The conference opened on Monday with the only tutorial of the week that had no competing sessions: “Creating Portable Stimulus Models with the Upcoming Accellera Standard.” Six speakers, all members of the Accellera Portable Stimulus Working Group (PSWG), presented a detailed update on the status of the emerging standard, including real code examples.
This was a major step up from the round of tutorials that the PSWG held last year, which covered mostly concepts and plans. It is great that the standard has advanced to the point that the speakers could show actual semantics and syntax. I thought that the material fit together very well, and that the speakers, including Sharon Rosenberg from Cadence, did a fine job. The room was absolutely packed; I counted upwards of 170 and heard that the official count was close to 200. There were numerous questions from the audience, in fact so many that the session chair had to ask some people to wait until after the tutorial so that it could finish on time.
“Accellera Day” continued on Monday with a lunch and a “town hall discussion” featuring several veterans of standards development. There were additional tutorials in the afternoon, but I was busy with press activities. Industry journalists and bloggers have noticed that portable stimulus is an area of interest and I was pleased to be able to share my experiences working on products in this domain and serving as Secretary of the PSWG. I expect to see some editorial articles coming out over time and will provide pointers when appropriate.
The other tutorial that I attended was on Thursday, sponsored by Cadence. “Reinventing SoC Verification – It Is About Time” covered many of the recent advances that we have made across our system and verification product line, both new product offerings and new technologies that link them together. Topics included advanced formal techniques, portable stimulus, metric-driven verification, and optimal use of multiple verification platforms. There was a special focus on parallel simulation, highlighting our new Xcelium Parallel Simulator announced on Monday. This tutorial was well attended, and the questions from the audience showed that there were clearly following the material and thinking about how they could apply new tools and techniques on their own projects.
There were a bunch of interesting-sounding technical sessions in between, although I attended only a few due to talking with the press and helping staff our booth in the exhibit hall. I enjoyed the keynote address from Cadence’s Anirudh Devgan, Senior VP and GM, Digital & Signoff Group and System & Verification Group. I appreciated his specific mention of how our Perspec portable stimulus solution can keep our fast new Xcelium Parallel Simulator well-fed with system-level use cases. Of course, we can generate tests for many Cadence verification tools, including the Protium S1 FPGA-Based Prototyping Platform that we also announced on Monday.
I was rather disappointed in the “Ride with The Verify Seven” evening panel sponsored by the Electronic System Design Alliance. Leaders from six small verification companies and well-known investor Jim Hogan talked about the rewards and challenges of being in an EDA industry dominated by much larger players. The topics covered were too broad, and the time consumed for panelist “position statements” didn’t leave enough left for questions. Still, I liked the concept and would welcome a more focused version at future events.
The second panel I attended, “Users Talk Back on Portable Stimulus,” did focus on a particular topic, and my favorite one. Users of in-house and commercial portable stimulus tools discussed how the technology benefitted their projects. Some members of the audience questioned whether this new method was necessary and wondered what value it might bring to their projects. I hope that hearing actual users tell their stories would alleviate any concerns. Sure, any new technology sounds exotic at first, but in this case, there is already plenty of real-world experience with successful tape-outs to validate the approach.
Last but not least, I helped out in the Cadence booth for most of the exhibit hours. Perspec System Verifier was one of our featured products, with both a short presentation and a live demo available for the asking. As is typical in a highly technical conference, the exhibition hall was quiet when competing with sessions but busy during the evening receptions. I had some really interesting conversations and hope to eventually pick up some new customers from the show.
If you attended DVCon, please share your experiences with a comment or two below. Thanks in advance, and now let’s all set our sights on upcoming DVCon events in China, India, and Europe,
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