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This year’s CDNLive San Jose was another gem. Many great keynotes, customer presentations, and technical updates. There were several mentions of Machine Learning, both in general about the emergence of Artificial Intelligence in the world, and specifically on its application to EDA challenges. And there was a lot of focus on speed—the world’s first production proven parallel simulator, Xcelium, along with Protium S1 and Palladium Z1. But what stuck out for me was a Qualcomm presentation on their use of Perspec™ System Verifier.
Accompanying these presentations, focused on verification engines, were several others on productivity topics. vManager for improving verification team collaboration and closure productivity. And one of the newest topics, the generation of Portable Stimulus for SoC verification test creation productivity. The main advantages are the ability to produce large quantities of specifically designed stimulus for complex use cases and the ability to execute these use cases on multiple verification engines.
The presentation by Sanjay Gupta, Qualcomm Technology Inc was a highlight:
In his talk, Sanjay highlighted that their primary objective for adopting portable stimulus was to create scenarios that would have been hard to achieve using manual techniques. The sheer complexity of their multicore, cache-coherent, low-power SoCs present many permutations that require testing of complex interaction between processing cores, caches and SoC IP components, and Perspec provides the automation to manage the full scope of the tests they need to produce. The result: they generated scenarios that would be have been hard to achieve without Perspec scenario solving capabilities.
As they proceeded they also achieved other objectives for improving test case throughput, productivity, and scenario coverage, as well as test case quality and ease of debug. They needed to create tests that were reusable from IP to sub-system, to SoC, and including software layers, along with portability across verification platforms and projects. They were also able to generate long meaningful tests with dynamic runtime controls embedded in tests, such tests were useful in fast platforms. Such tests caught several interesting SoC bugs that Sanjay described in some detail.
Because their SoCs share many common sub-systems, they have produced one model that supports multiple chip types, SoCs and sub-systems, and verification focus areas. The model easily is maintained along with reusable test plans that can be applied across various projects, which are integrated with the planning and management creation tool, vManager.
Cadence is actively driving the Accellera Portable Stimulus Specification based on their donation from Perspec System Verifier’s scenario modeling notation. This standard is due for review release at DAC 2017.