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Multi-core, coherent SoCs are very complex and verifying their behavior requires a system level perspective that is not easily acquired. As more devices incorporate the coherent multi-core architecture out of competitive necessity, organizations are grappling with the challenges of achieving high quality. This presents a unique opportunity for Cadence to provide libraries for use with the Cadence Perspec System Verifier that address these complex system level behaviors, and reduce the project risk and verification effort.
The notion of standards-based verification IP became popularized with the publication of the Verification Reuse Methodology by Verisity. An industry was born, and now everyone purchases Verification IP for their projects to leverage protocol expertise and reduce overall verification time. With the publication of the new Accellera Portable Stimulus Standard the industry is on the cusp of a new kind of of verification IP for system level functionality, the interactions of multiple components. These system level behaviors (low power, cache coherency, etc) require an SoC architect's knowledge and the verification architect's strategy rolled together. System Verification IP can do that for these complex and common SoC structures and benefit the overall industry.
Cadence has invested in developing a library of portable stimulus designed for specific functional subsystems common in complex SoCs. The first available library is for multi-core ARMv8 and ARMv8.2 architectures. These libraries come with a verification plan for measuring completion of verification, and self-checking scenarios to test the complex interaction in compute subsystems of low power management, coherency operations, different exclusive locking schemes, and system page management. More libraries are in use by early adopter customers and will be announced later this year.
Read more details about the ARM library in a blog by Nick Heaton on the ARM Community site.