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This approach not only avoids an expensive library characterization, which only provides estimates of the component delays, but also has the advantage of using the synthesized components in the context of the actual design. This is done using CtoS's built-in RTL Compiler synthesis engine and the provided .lib file to synthesize and analyze the timing of the generated RTL from which CtoS gets accurate feedback to refine the scheduling of components.
The end result is higher quality RTL with more aggressive resource sharing that once synthesized, meets the timing requirements in the targeted technology.
This Team ESL posting is provided by Dr. Sergio Ramirez, Sr Staff Product Engineer for the C-to-Silicon Compiler high level synthesis product.