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John Blyler, Editorial Director at Extension Media, presented in our EDA360 Theatre at DAC 2012 about "ASIC/ASSP Prototyping with FGPAs" and provided an update on his annual survey on this topic. The current 2012 survey is actually currently ongoing and you can still participate here.
FPGA-based prototyping is the fourth pillar in the Cadence System Development Suite. The unique advantage of the Cadence solution, called Rapid Prototyping Platform (RPP), is its proximity to the Palladium XP Verification Computing Platform (VCP) and the application of the same ASIC front-end flow (as opposed to FPGA centric flows in roll-your-own or other commercial offerings). The big issue in FPGA based prototyping is the bring-up time, which is often dominated by making sure before actual bring-up that after all modifications to an RTL stop, one actually still has the same functionality that was put into the flow. In the Cadence flow the netlist targeted to the RPP can be used on Palladium without modification, allowing more efficient verification. Together with applying an ASIC optimized flow, automated partitioning and the re-validation on Palladium, the typical bring-up time of four to six months for roll-your-own solutions and other commercial offerings can be reduced to weeks.
So what does FPGA prototyping enable? In the System Development Suite vision, the focus of FPGA based prototyping is software development and running verification regressions. While its speed is in the range of 10s of MHz, faster than emulation which is in the MHz range, its debug observability into the hardware is much more limited. Software debug feels similar to debug on the development board with the actual chip, because it is using standard JTAG connections and standard software debug environments. Because it is available well before silicon, it definitely beats having to wait for the actual chip to be plugged into the development kit when it becomes available. Finally, due to its speed, letting FPGA based prototypes run in the actual live environment of the chip under development and connect to real world interfaces like Bluetooth, Ethernet, USB etc. becomes a whole lot easier.
That's our story ... so how does it compare to actual user priorities? Quite ,actually, according to surveys! John Blyler ran a survey for a couple of years now. Survey questions focused on demographics, end-user application markets, design specifications, tool usage, verification types, methodologies and prototyping techniques. In John's 2010 survey, conducted in October 2010, a total of 110 filtered designers (taking out Universities etc.) participated in this survey. When asked "If you are using or are planning to use FPGA based prototyping, please describe the use mode," the responses looked as follows:
The largest number of respondents referred to "HW/SW Co-Design and Co-Verification" as their main use model, loosely followed by HW/Chip verification. If we add in "System Validation" and "System Integration" - both involving the software and the hardware - and the actual "Software Development," then the use models closely involving software definitely have a leg up.
The other use model that's interesting here is the 30% of respondents identifying "IP Development and Verification." Given the complexity of the chips which we are talking about prototyping here, verifying the IP or the sub-systems to be integrated into those chips definitely is an attractive use model. Note that software may play a role here, especially when it comes to sub-system verification involving processors.
The last use model - Post Silicon Debug - is interesting in itself as well. All prototyping techniques - virtual, emulation and FPGA-based -- have their place even after silicon is available. The better controllability compared to the actual chips are probably the central driver here.
Bottom line, it looks like the results of this survey confirm the vision of the System Development Suite we have been working towards. Software related use models and verification are the main drivers. It will be interesting to see whether the trend continues, so please help John Blyler and us by providing input to the most recent 2012 survey here!
I will make sure to update you on the results when I have them.