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When Freescale wanted to measure the coverage of their validation test suite for their automotive products, they determined that that the memory map coverage approach wasn’t adequate. They needed a different way to enable coverage collection. They decided to port their post-silicon code into a pre-silicon environment and use the native coverage support of the Palladium XP platform to score their tests. This unique coverage support helped them augment the coverage of verification test suite as well as measure the coverage of the validation test suite. They identified coverage holes and filled it with new tests, or enhanced existing tests. In addition, redundant tests were removed or run with lower priority in order to speed up the regression tests while simultaneously increasing test coverage. With the ability to merge coverage between simulation and acceleration runtime environments, Freescale was able to achieve a more holistic assessment of the test coverage.
Check out Freescale’s presentation titled ‘Introducing coverage driven validation using Cadence IXCOM flow.”
Also, watch this video, where Amitesh Khandelwal, a Freescale Semiconductor design manager working on verification and validation domains, talks about the different challenges his organization faced in its SoC environments, from the lack of synergy and reuse to gaps in coverage in its test cases. With the Palladium XP platform, Freescale has gained critical coverage of the gap as well as a solution to quickly find critical bugs.
Technology Spotlight – Coverage in Palladium XP Series
The Palladium XP platform has an industry-first and unique capability to natively score different types of coverage directly in its hardware. This capability helps customers resolve answering certain frequently asked questions around coverage closure at the sub-system and system levels. Some of these questions are captured in the diagram below.
With the Palladium XP platform’s coverage feature, verification and validation engineers can perform SoC integration verification, identifying the activity between sub-blocks or activity at the top levels of their design. Customers can verify system-level modes of operation, identifying, for instance, whether two processing units are simultaneously active or whether interrupt was issued when the CPU transferred data to the GPU. They can correlate coverage to design features that they are testing and measure progress against their overall verification plan. And, as in the case of Freescale, they can improve the hardware coverage of the software tests, exploring how much of their RTL is being exercised by their software test and then deciding if they should improve their software tests to achieve higher RTL coverage score.
Furthermore, users frequently want to score coverage in several engines. For instance, in RTL simulation, simulation acceleration or in-circuit emulation. All of the coverage capabilities can be merged into a single coverage database to provide a more holistic assessment of design coverage.
To learn more about the Palladium XP verification computing platform’s coverage features, contact your Cadence sales or applications team.
Author notes: This article is part of a series of "double-take" articles aimed at highlighting an actual user application of a Palladium XP use model, along with a technology highlight leveraged in the application.