System Design and Verification Blogs

DFT (Design for Testability) provides the much-needed support to the manufacturers to catch up with the increasing demand and pressure for mass production. It helps produce chips with flawless design and perfect quality for challenging applications.

Traditionally it is completed in a simulation environment which is a very time-consuming task.

To reduce the verification time and accelerate the process, Enflame, in collaboration with Cadence, developed an emulation environment using a Palladium emulator and a virtual JTAG solution. The solution helped Enflame create functional ATE test vectors besides scan and MBIST, which improves ATE test coverage and speeds up the silicon bring-up process. Enflame, achieved savings in time and speed improvements up to 5000X as compared to simulation.

This blog will focus on the emulation testbench setup, test vector development, and DFT/DFD simulation acceleration flow.

DFT/DFD Simulation Challenges

• Emulation acceleration and coverage 

  With the growing complexity and larger size of SOC design, emulation verification becomes more challenging. For larger designs, it may take even months. So, accelerating emulation with improved coverage during the pre-silicon phase is a challenge.

• ATE test vector development and debug

  Limited testing due to longer emulation time results in insufficiently verified test vectors many times. It makes debugging difficult and often results in increased cost, time, and effort. It is challenging to develop SCAN/BIST test patterns.

• DFD feature Verification and debug Tools development

Solution

Such requirements motivated Enflame to build up an ATE-like environment for running ATPG or memory BIST patterns during the pre-silicon stage. Enflame built a perfect prototype verification environment at the pre-silicon stage based on Cadence Palladium to verify the chip's function and performance.

It helped Enflame accelerate the simulation on both RTL and netlist levels and allowed them to complete validation of test vectors and DFT/DFD logic before tape-out.

The feature development and verification for all debug tools were also completed during the pre-silicon stage.  It used Cadence Speedbridge,  DFI interface, and HBM2E for PCIe and memory model. The MC controller is connected to DFI PHY through DFI interface. The virtual JTAG on the bottom also adopts Cadence's solution.

To produce JTAG sequences and perform signal interaction with DUT, Enflame developed a transaction-based solution in collaboration with Cadence. The virtual JTAG Solution is based on Lauterbach Trace32.

Advantages

• It does not rely on the JTAG hardware debug box.
• It helps in quickly building a JTAG work environment and facilitates early DFT verification and tool development.
• It can function as long as there is a license. So, it can support more concurrent users.

The Enflame debug box is a framework with a set of tools to be used together and supports debug management. The physical JTAG solution is used in ICE mode. Its strength lies in that it's a real debug device, which is completely consistent with the lab environment for silicon testing.

The ATPG Scan Solution is composed of two parts:

• RTL testbench, which is automatically generated by a script tool developed by Enflame. The test bench contains a huge SRAM for storing test patterns. Before a test starts, in the runtime phase for database configuration, we need to first preload the pattern to the SRAM, and then label a DFT test for obtaining the final test results.
• For the control part, transmission is done through the JTAG interface.

ATPG emulation testbench generator is developed in collaboration with Cadence. It's a set of tools based on python. We conducted a mixed compilation and compiled everything into the Palladium database. So, this environment adopts a standalone user mode, and no peripheral interface is required.

Memory BIST and repair solution. In fact, ATPG can also be used for memory BIST, but since the pattern size for memory BIST is relatively small, a virtual JTAG solution is used here.

The SRAM involved is a memory label generated with the help of a set of tools developed by Cadence and supports:

• Normal Read/Write a function
• Error injection
• Built-in-scan chain
• Complete memory repair sequence
• Error Injection
  • MBIST and repair info generation
  • Boot Sequence and memory repair

Results

The use-cases introduced in the emulation environment to ascertain the effectiveness of the above solutions are as below.

ATPG scan 

Below cases were considered to display the efficacy during emulation of ATPG scan:

• SOC initialization and configuration pattern and work mode switch,
• AC Scan pattern and OCC insertion functional verification
• DC Scan pattern and OCC insertion functional verification.

It has been found that, in comparison with simulation, the ATPG scan is about 4000 times faster for AC (Delay) scan. According to our test results, it is about 5000 times faster for DC (Stuck-at) scan.

ATE Test Vector

For emulation of function ATE test vector, below three examples test vectors were considered:

• Vector 1: Block-level DC Serial scan test pattern with pattern count of 3427
• Vector 2: Block-level AC scan test pattern with pattern count of 38315
• Vector 3: SOC level Serial Chain test pattern testing one block with pattern count 276

Compared with simulation, about 80 hours (about 3 and a half days) are saved for vector 1, about 480 hours (about 3 weeks) for vector 2, and about 10 hours for vector 3.

MBIST and Repair

Below are the use cases for MBIST and repair:

• Verification for BIST logic function.
• BIST Pattern 1 is extraction and verification of repair info
• BIST pattern 2 is bootup fuse info distributed to BIST repair register
• BIST pattern 3 is ATE pattern generation on EMU
• BIST pattern 4 is the verification of fault injection and repair info used in the lab

The impact of this scheme as it shows significant improvement as shown in the performance chart below.

It resulted in 1000X speed improvement for pattern1, and the time was reduced to 20 minutes as compared to 2 weeks in simulation. For test pattern 2 it demonstrated 2000X speed improvement along with fast turnaround to find any bootup risk. It also proved effective with 1000X and 800X speed improvement for test patterns 3 and 4.

Conclusion

It has been found that, in comparison with simulation, the ATPG scan is about 4000 times faster for AC (Delay) scan and about 5000 times faster for DC (Stuck-at) scan, also timesaving up to 480 hours (about 3 weeks) was achieved by using the proposed scheme.

Learn more

• Best Verification Throughput for Pre-Silicon Verification and Debug
• Cadence System-Level Verification IP