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You might have thought it would be “just another DAC” this year, again in Austin, where the food and live entertainment is undeniably superb. But wait, there’s help for improving verification of your cache coherent multi-core SoC, one of the biggest challenges for today’s mobile and server verification teams. This year’s DAC holds several opportunities to learn how to make improvements, and specifically how Cadence Perspec™ System Verifier can transform your verification effectiveness and address these challenges.
Figure 1: Today’s big SoC verification challenges
Below is a list of ways you can get access to the information you need:
Mike Stellfox, Sharon Rosenberg, and Larry Melling are available for customer meetings and demos. Come to the booth and ask for them by name!
Monday, Tuesday, and Wednesday, in Cadence booth: #107
Mike Stellfox, Verification Fellow, Cadence, will be on a panel discussing Smarter Verification. Moderated by Ann Mutschler, SemiEngineering.
This panel will review the requirements for verification in an increasingly application-specific and connected world, and examine the key trends in verification productivity within both the core engines and verification fabric, including the trends for next-generation debug, machine-learning-based data analytics, automation of test-case creation, and continuous integration of hardware and software.
Monday, June 19th, 12:00-1:30pm, Verification Luncheon, Ballroom B/C
Sharon Rosenberg, Solution Architect, Cadence, will be a presenter in an Accellera tutorial: “An Introduction to the Accellera Portable Stimulus Standard”.
This standard is important for the industry and is expected to facilitate rapid deployment of supporting technologies in the market. Don’t miss out on this important educational opportunity!
Monday, June 19th, 1:30-3:00pm, Accellera Portable Stimulus Standard (PSS) Tutorial, Room 18CD
Sanjay Gupta, Director of Engineering, Qualcomm, will present “Efficient Verification of Mobile SoCs with Perspec and Portable Stimulus”
Sanjay originally presented this topic at CDNLive Silicon Valley, April 2017 – read about it in this blog. He’ll give an updated presentation about their objectives, achievements, and intentions.
Monday, June 19th, 4:00pm, Cadence DAC Theater, booth #107
Mike Stellfox, Sharon Rosenberg, and Larry Melling will be available at our Expert Bar to discuss SoC Verification, portable stimulus, and if you wish they can share about Perspec System Verifier. These are held in the Cadence booth #107:
Here is the complete DAC 2017 Expert Bar schedule.
Perspec System Verifier produces stimulus for SoC Verification that is portable on multiple verification engines across Xcelium, Palladium, Protium, and post-silicon. Customers are struggling to plan, create, and maintain thousands of SoC use case tests for today’s large scale SoCs. It requires multiple disciplines, team members, to participate, and the work is manual and error prone. Perspec System Verifier generates tests automatically, enabling an SoC team’s systematic verification strategy of implementing the most crucial top-down use case tests.
While other tools depend on the user to capture those use cases, Perspec uses the input model specification and the desired test scenarios to interpret the possible use cases to test, while providing self-checking schemes, collecting coverage and providing runtime operators for test reactiveness. This makes the input model more easily maintainable, and is why the Accellera Portable Stimulus Specification is significantly based on this approach. There is already a working version of Perspec supporting the draft of the language standard.
The emergence of the Accellera Portable Stimulus Specification (PSS) draft language standard is big news for the verification industry. See Perspec demoing a running version of the PSS draft language. Perspec can run the DSL and C++ library input formats and mixes the two. This is an opportunity for the audience to see the emerging Accellera PS in action!
Another important feature of the product is the out-of-the-box verification library for ARM multi-core SoCs. This library, which is widely used by Perspec customers, targets multiple SoC level aspects such as cache coherency, distributed virtual memory and low power etc... This library enables immediate Perspec test generation for ARM-based SoCs, reducing the time for verification teams to ramp up and deploy Perspec on their projects. Come and learn about the coherency / low power system verification IP for ARM provides out-of-the-box test generation for generating tests in Perspec for the extremely complex behaviors of a multi-core cache coherent SoC.
Figure 2: Perspec System Verifier for SoC Verification