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Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager™ Metric-Driven Signoff Platform, and the Cadence Palladium® Z1 Enterprise Emulation Platform to improve their performance validation flow. They were looking for a better way to analyze their performance results so trade-off decisions could be made faster—a task well suited to Interconnect Workbench. Each new generation of their microcontroller units (MCUs) was more complex than the last, but the time-to-market constraint was more or less the same. This meant that they were getting bottlenecked by analytics, and it was causing strain on their design flow.
The largest advantage Renesas saw with the Interconnect Workbench was with its ability to give performance verification at multiple levels. The Interconnect Workbench was used to characterize and measure the latency of the MCU interconnects and bandwidth-critical paths, apply defined traffic loads, measure performance of traffic inside the MCU, and more.
The Interconnect Workbench was also used for testbench automation, which involves a single-step process to convert the metadata in a CSV file into Universal Verification Methodology (UVM) analysis and functional verification testbenches. From there, the Interconnect Workbench automatically generated a testsuite that drive initial traffic for performance analysis and functional verification.
All of this combined to allow Renesas to do more of their debugging and addressing of performance challenges earlier in the design cycle. It increased the number of times they could iterate on the interconnect configuration to achieve their performance goals, and overall reduced their time-to-market for this step by weeks.
By adopting the Cadence Interconnect Workbench, Palladium Z1, and other associated tools, Renesas cut their analysis and setup times from 22 to nine days, reduced execution time by 250X, all while verification coverage.
To read the full Renesas Interconnect Workbench customer story, click here.