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Mediatek has been using the Cadence Perspec™ System Verifier for their SoC level verification. At a recent CDNLive, Mediatek reported on their experience with Perspec and the results from their first phase of deployment. Their primary goal in adopting Perspec is to improve verification efficiency for their line of complex mobile application processor SoCs, each employing an ARM-based multi-core, cache-coherent CPU sub-system. The results of applying Perspec include improvement in regression efficiency and quality, enabling hardware/software co-verification, reducing debugging time, and increasing code and functional coverage at the SoC level.
Figure 1: Verification Challenges of ARM-based Multi-core, Cache-coherent SoC
One of the important measures of SoC level verification efficiency is creation of tests in a manner that they are reusable. The intended benefits of portable stimulus is to improve SoC level verification efficiency, and Accellera has an active Portable Stimulus Working Group chartered with defining a standard. Read about the recently released draft of the Portable Stimulus Standard (PSS) here, and watch a demonstration here.
Portable stimulus enables the reusability of tests, as illustrated in Figure 2, along four dimensions of reuse: vertical, horizontal, use-case, and project to project. Each dimension of reuse provides verification efficiency benefits by reducing the effort for the creation of tests.
Figure 2: Four Dimensions of Test Reuse
Cadence Perspec System Verifier
Perspec takes as one input the reusable cases or scenarios as described by different users. These scenarios are described in an abstraction that is not implementation dependent, and can be mastered by different members of the team including Architects, HW Designers, SW Developers, SW Test Engineers, and Post-silicon Validation Engineers (other titles may apply as well). The tests generated by Perspec are executed on the embedded CPU(s) in the target SoC. They are generated and coverage can be measured for the tests generated, and separately for the tests that are executed. See Figure 3 for some example test use cases showing data flowing from the CPU sub-system to various interface sub-systems.
Figure 3: Perspec System Verifier Realizes the Concept of Portable Stimulus
Figure 4 captures the steps of applying Perspec to verify an SoC. Perspec uses a model-based approach, where the model includes actions, input and outputs, declarative resource availability, exec blocks, and activities with data and control flow. This approach was adopted by Accellera to become the Portable Stimulus Standard, recently released for review at DAC 2017.
The model describes the system under test, and can include pre-packaged libraries, such as the Cadence CPU Coherency Library for ARM CPU sub-systems. The use cases, or scenarios, describe the operations or data paths of the system that a test should include and are abstract to allow elaboration of all possible implementations of the use case in the system under test.
Figure 4: Perspec System Verifier Generates Tests for Different Platforms
Part 2 of the blog can be found here.
For more information, visit the Perspec product page.