System Design and Verification Blogs

Here we go through the application of Cadence Perspec™ System Verifier by Mediatek for their SoC level verification. In case you missed it, Part 1 of 3 can be found here.

As shown in Figure 5, the tests are generated automatically from the model and a corresponding scenario. Each test is automatically adapted to the target verification engine, whether a virtual platform like the Virtual System Platform, an RTL simulator like Xcelium, an emulator/accelerator like Palladium Z1, an FPGA prototype like Protium S1, or a silicon board with the final chip.

Figure 5: Detailed Views of Usage Flow

Coverage of generated tests and executed tests are collected and can be analyzed against the verification plan in the vManager Metric-Driven Signoff Platform. Figure 6 shows debugging of the use case scenarios can be done in the Indago Portable Stimulus Debug app, providing an interactive view of the UML activity diagram for the test code, a core waveform view showing overlap of actions, the Smartlog of action entries and exits, all fully synchronized.

Figure 6: Indago Portable Stimulus Debug Integrated Debug Environment

Mediatek Application

The results of the initial deployment by Mediatek can be seen below in Figure 7. The main goal was to focus on the CPU sub-system and measure the improvement in verification efficiency. Their Key Performance Indicators (KPI) were; a) productivity of creating random and directed-random C tests per day; b) debugging time; and c) an increase in code and functional coverage.

Figure 7: Mediatek Goal and Expected Impact on Key Performance Indicators

The first step was creating the model of the Mediatek SoC. Since they wanted to focus first on the CPU sub-system, the instantiated the Cadence CPU Coherency Library for ARM CPU sub-systems, and began modeling the other resources they wanted to include in those tests. Figure 8 shows these in the Library on the left, and the details in the middle. Solving the model in Perspec produces the UML chart on the right, showing the various system resource relationships and concurrencies.

Figure 8: Mediatek Model and Scenario Development

Part 3 of the blog is here.

For more information, visit the Perspec product page.

Steve