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If you are attending the Design Automation Conference (DAC 2012) June 4-7 in San Francisco and you are interested in SystemC/TLM driven design and verification, including high-level synthesis, there are a lot of interesting sessions.
First, there is a parallel conference going on Saturday and Sunday (June 2/3): ESLsyn 2012 - the 2012 Electronic System Level Synthesis Conference
Then there is a two hour tutorial led by Michael Bohm of Intel: Synthesizing SystemC to Layout, which is being offered starting at 8:30, 11:30, and 3:30 on Monday June 4th. Mike is one of the leading experts on both high-level synthesis as well as SoC design methodologies, so it will be a great opportunity to learn how to deploy this in the real world.
Speaking of deploying HLS in the real world, there will be a lively panel discussion - High-Level Synthesis Production Deployment: Are We Ready? This panel is led by Clem Meas and features panelists from Intel, Freescale, Xilinx, NEC, Calypto, and Cadence's own Mark Warren. It happens at 9am on Wednesday June 6th, and provides a good reason to leave the Denali Party before last call.
Later on Wednesday, from 1:30-6:00pm is the North American SystemC User's Group, which features topics on TLM design and verification, as well as a presentation by Cadence's Stuart Swan along with Jerome Cornet of ST on modeling virtual platforms with TLM.
Finally, there is a research paper session - High-Level Synthesis is Not Just About Translation! chaired by Satnam Singh of Google, from 3:30-5:30pm on Thursday June 7th.
That's all without even mentioning the Cadence demo on TLM-driven design and verification, which runs Monday at 3pm, Tuesday at noon, and Wednesday at 1pm and 5pm. We will be talking about how to deploy higher-level design and verification in a production flow.
I'm looking forward to a fun-filled week in San Francisco. If you are interested in learning how we're working with customers to deploy these technologies in production, come on by the Cadence booth and ask for me.