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  • tomacadence
    Portable Stimulus Shines at DVCon
    By tomacadence | 4 Mar 2017
    For me, this week was almost entirely consumed with the Design and Verification Conference and Exhibition ( DVCon ) at the familiar DoubleTree in San Jose. The hotel has replaced its chandeliers with shiny new space-age fixtures, but otherwise, I felt at...
    0 Comments
    TAGS:
    uvm | prototyping | pswg | Acceleration | Functional Verification | Perspec | System Design and Verification | Palladium | SoC | Emulation | Simulation acceleration | DVcon | Accellera | metric-driven verification | Hardware/software co-verification | portable stimulus | simulation | verification
  • tomacadence
    What Sort of Bugs Does Portable Stimulus Find?
    By tomacadence | 17 Feb 2017
    In a recent blog post , we discussed some general concepts of bugs, problems, issues, and features. We gave examples of different types of bugs typically found during the functional verification of chip designs, and made the claim that “portable stimulus...
    0 Comments
    TAGS:
    hardware-software co-verification | uvm | Low Power | pswg | debug | Functional Verification | System Design and Verification | embedded software | Emulation | Accellera | Hardware/software co-verification | debugging | portable stimulus | interrupts
  • tomacadence
    Preview of an Exciting DVCon
    By tomacadence | 2 Feb 2017
    In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest annual event for the industry. Nothing against DAC, but if you’re involved in functional verification as I am, the Design and Verification Conference and Exhibition (...
    0 Comments
    TAGS:
    uvm | prototyping | pswg | Acceleration | Functional Verification | Perspec | System Design and Verification | Palladium | SoC | Emulation | Simulation acceleration | DVcon | Accellera | metric-driven verification | Hardware/software co-verification | portable stimulus | simulation | verification
  • tomacadence
    Bare Metal Tests and Hardware-Software Co-Verification
    By tomacadence | 23 Jan 2017
    One interesting question that arises from time to time is whether the Cadence® Perspec ™ System Verifier can verify software as well as hardware. The question is simple enough, but the answer is more complex. There are at least two versions of “yes...
    0 Comments
    TAGS:
    hardware-software co-verification | uvm | pswg | Acceleration | Perspec | virtual platform | System Design and Verification | Emulation | System simulation and analysis | Accellera | FPGA prototypes | testbench | portable stimulus | silicon | bare metal | verification
  • tomacadence
    Bugs, Problems, Issues, and Features
    By tomacadence | 4 Jan 2017
    There’s no better way to demonstrate the value of a verification tool than to find a killer bug in the customer’s design. When the verification engineer looks up from the screen and says, “Wow – we might never have found that!” we EDA vendors are equally...
    0 Comments
    TAGS:
    performance | uvm | pswg | Functional Verification | Perspec | OVM | issue | bug | feature | Accellera | Problem | portable stimulus
  • tomacadence
    Report From the 17th MTV Workshop in Austin
    By tomacadence | 20 Dec 2016
    Austin is always a nice place to visit, and last week I spent a few days there to attend the 17th International Workshop on Microprocessor and SOC Test and Verification ( MTV ). The event is held on the top floor of the Hyatt Regency Hotel, with spectacular...
    0 Comments
    TAGS:
    security | Perspec | Safety | formal | workshop | SoC | Test | ISO 26262 | MTV | power | microprocessor | portable stimulus | verification
  • tomacadence
    Perspectives on Developing EDA Standards
    By tomacadence | 6 Dec 2016
    Last week, my colleague Paul McLellan published a blog post on the standardization work underway within the Portable Stimulus Working Group ( PSWG ) of Accellera Systems Initiative. He did a nice job of describing portable stimulus as the PSWG defines it...
    0 Comments
    TAGS:
    uvm | 1394 | pswg | Perspec | OVM | USB | IEEE 1500 | Accellera | VCX | VCi | PCI | portable stimulus
  • tomacadence
    A Personal History of Functional Verification
    By tomacadence | 18 Nov 2016
    In my most recent blog post , I summarized some of the key points from an October presentation at DVClub Silicon Valley by Dave Brownell from Analog Devices. As part of his introductory section on the motivation for the industry to move to portable stimulus...
    1 Comments
    TAGS:
    ASIC | uvm | pswg | formal. Verisity | Functional Verification | System Design and Verification | OVM | System Development Suite | constrained-random | Simulation acceleration | Accellera | metric-driven verification | Virtual Platforms | Hardware/software co-verification | simulation | FPGA | System Design and Verification
  • tomacadence
    Analog Devices Promotes Portable Stimulus at DVClub
    By tomacadence | 3 Nov 2016
    If you’re not familiar with the series of DVClub events held in North American, Europe, and Asia, please consult my most recent blog post for a brief history. These events offer a unique opportunity for hands-on verification engineers to network...
    0 Comments
    TAGS:
    Analog Devices. ADI | pswg | cadence | debug | System Design and Verification | Dave Brownell | software | Accellera | System Design & Verification | portable stimulus | System Design and Verification | verification
  • tomacadence
    DVCon(x2), DVClub(x2): Portable Stimulus Is Everywhere
    By tomacadence | 21 Oct 2016
    In my most recent blog post , I talked about the industry vision for portable stimulus as a way to improve verification reuse, automate test creation, and enhance coverage. The Accellera Portable Stimulus Working Group (PSWG) is working hard on a standard...
    0 Comments
    TAGS:
    horizontal reuse | DAC | uvm | prototyping | pswg | Perspec | System Development Suite | DVClub | Emulation | DVcon | Accellera | portable stimulus | simulation | System Design and Verification
  • tomacadence
    The Industry Vision for Portable Stimulus
    By tomacadence | 7 Oct 2016
    As I mentioned in my last blog post , portable stimulus is one of the main areas of focus for me at Cadence. Paul McLellan has published two excellent posts about Perspec System Verifier, our product offering in the space, but for today I’d like to take...
    0 Comments
    TAGS:
    uvm | pswg | Acceleration | Perspec | virtual platform | System Design and Verification | Emulation | System simulation and analysis | Accellera | FPGA prototypes | testbench | portable stimulus | silicon | verification
  • tomacadence
    Back in the Saddle Again
    By tomacadence | 23 Sep 2016
    Nearly five years ago, I signed off with my last blog post in the Cadence Community. I’m delighted to return to the Cadence family and to resume my blogging activity. My former colleagues have welcomed me back warmly, and I hope that those of you who...
    0 Comments
    TAGS:
    pswg | Perspec | System Design and Verification | System simulation and analysis | Accellera | portable stimulus | System Design and Verification | verification
  • fschirrmeister
    How to Maximize Your Verification Experience at DAC 2016
    By fschirrmeister | 2 Jun 2016
    Next week will mark the annual EDA gathering in Austin. For me it is my 20 th DAC … I know, compared to some I am still wet behind my ears, but that’s only because I started my career in embedded software and actual chip development. I already outlined...
    0 Comments
    TAGS:
    dac2016 | DAC | Verification Computing Platform | Protium | Palladium | Prtable Stimulus
  • rmathur
    Cheating Tetris
    By rmathur | 24 Nov 2015
    Remember Tetris? We’ve all played it at some point in our lives. You know, the game with falling blocks of different sizes and shapes where you have to place the incoming blocks in an optimal way to make full use of the available open spaces. Well, once...
    0 Comments
    TAGS:
    Verification Computing Platform | Palladium | Tetris | Emulation
  • fschirrmeister
    Accelerating the Next Big Shift in Verification
    By fschirrmeister | 8 Sep 2015
    Today Cadence announced that we are aligning our proposal to the Accellera Portable Stimulus Working Group (PSWG) with the other two commercial vendors in this market – Mentor Graphics and Breker – to deliver a joint contribution, intended to accelerate...
    0 Comments
    TAGS:
    pswg | scenario | UML | software-driven verification | Accellera
  • rmathur
    Double-Take: Improving Validation Test Suite with System-Level, Coverage-Driven Verification
    By rmathur | 31 Jul 2015
    Application Spotlight When Freescale wanted to measure the coverage of their validation test suite for their automotive products, they determined that that the memory map coverage approach wasn’t adequate. They needed a different way to enable coverage...
    0 Comments
    TAGS:
    validation test suite | Freescale | Coverage-Driven Verification | Palladium XP | verification
  • fschirrmeister
    Use Model Versatility Is Key for Emulation Returns on Investment
    By fschirrmeister | 20 Jul 2015
    It is always great to see when customers confirm what we in product management put forward as key elements for our product. As my team owns the product management for emulation, DAC 2015 in San Francisco was once again a great opportunity to check in...
    0 Comments
    TAGS:
    ROI | use models | Emulation | DAC 2015 | System Design and Verification
  • fschirrmeister
    DAC 2015 – Join Us to Experience the Continuum of Verification and System Development Engines!
    By fschirrmeister | 4 Jun 2015
    The biggest yearly event in electronic design automation (EDA) is due to take over San Francisco next week, together, apparently, with the Apple developer community, to take over the Moscone Convention Center. This is the first DAC at which all three...
    0 Comments
    TAGS:
    cadence | EDA | Moscone Center | DAC 2015 | verification | system development
  • rmathur
    Double-Take: Power Event Monitoring and In-Circuit Acceleration
    By rmathur | 20 Feb 2015
    For a number of years now, AMD has been applying an advanced acceleration use case referred to as hybrid verification. It’s basically a verification run utilizing the strengths of two verification engines -- in this case, a virtual platform and an emulation...
    0 Comments
    TAGS:
    power event monitoring | Verification Computing Platform | system-level validation | hybrid verification | hardware assisted verification | Palladium XP | Emulation | in-circuit acceleration
  • rmathur
    Code Coverage at the System Level with Hardware-Assisted Verification? Are You Kidding? (Part I)
    By rmathur | 9 Dec 2014
    Short answer: Nope, not kidding. You can get value from applying code coverage with hardware-assisted verification by focusing on actionable data. Longer answer, keep reading below to learn more. Functional coverage is a technique to verify that a design...
    0 Comments
    TAGS:
    hardware-assisted verification | code coverage | functional coverage | verification closure | verification
  • rmathur
    Code Coverage at the System Level with Hardware-Assisted Verification (Part II)
    By rmathur | 3 Dec 2014
    In yesterday’s Part I blog post , I talked about a technique for focusing code coverage efforts on actionable data—namely, focusing on higher level connectivity. Here, let’s discuss a second technique to support system-level code coverage with hardware...
    0 Comments
    TAGS:
    hardware-assisted verification | code coverage | system-level code coverage | coverage analysis | functional coverage
  • fschirrmeister
    Looking Back at a Great Week for System Design!
    By fschirrmeister | 5 Oct 2014
    Reflecting on last week at ARM TechCon, together with our close partner ARM, we had a great week for System Design! You can see an overview of all our activities at TechCon 2014 here . First, on Monday, we announced the extension of our partnership to...
    0 Comments
    TAGS:
    debug | System Design and Verification | embedded software | hybrid | ARM TechCon 2014 | ARM | verification
  • fschirrmeister
    Cadence Palladium Platform and ARM Fast Models - Making the Future the Present
    By fschirrmeister | 2 Oct 2014
    In its 10 th year now, ARM TechCon is in full swing this week at the Santa Clara Convention Center. Being an engineer in a specialized field, it is sometimes difficult for me to explain to family and friends what I actually do. I have used several analogies...
    0 Comments
    TAGS:
    NVIDIA | Palladium | hybrid | Emulation | ARM Fast Models | ARM
  • SumeetAggarwal
    The webinar on “Effective system-level coverage” does an effective coverage of the talk
    By SumeetAggarwal | 5 Sep 2014
    If you're anything like I am, you listen to webinars with one ear, occasionally checking your computer screen if a graph or image is referenced, perhaps catching up on email or articles while the webinar is running in the background. I have always struggled...
    0 Comments
    TAGS:
    system-level coverage | PXP | hardware assisted verification | webinar | Palladium XP | hardware acceleration | EDA webinar | hardware accelerated verification
  • SumeetAggarwal
    Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption Kits
    By SumeetAggarwal | 7 Aug 2014
    The state-of-the-art Palladium XP hardware/software verification computing platform unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity. As impressive as the platform...
    0 Comments
    TAGS:
    ICE | sim accel | IXCOM | Palladium XP | COS Cadence Online Support | Simulation acceleration | hsv | RAKs | stb
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